公开(公告)号：US12057422B2

公开(公告)日：2024-08-06

申请号：US18145979

申请日：2022-12-23

Applicant: Kioxia Corporation

Inventor： Takahiro Tomimatsu ,  Shinya Arai

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/535 ,  H01L25/00 ,  H01L25/18

CPC classification number: H01L24/08 ,  H01L23/535 ,  H01L24/80 ,  H01L25/0657 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/08145 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2924/1431 ,  H01L2924/14511

Abstract: According to one embodiment, a semiconductor device includes a first substrate; a first insulating film provided on the first substrate; a first plug provided in the first insulating film; a second substrate provided on the first insulating film; and a first wiring including a first portion and a second portion. The first portion is provided in the second substrate and coupled to the first plug, and the second portion is provided on the second substrate and coupled to a bonding pad.

公开(公告)号：US11688726B2

公开(公告)日：2023-06-27

申请号：US17189955

申请日：2021-03-02

Applicant: Kioxia Corporation

Inventor： Yasunori Iwashita ,  Shinya Arai ,  Keisuke Nakatsuka ,  Takahiro Tomimatsu ,  Ryo Tanaka

IPC: H01L25/18 ,  H01L23/00

CPC classification number: H01L25/18 ,  H01L24/06 ,  H01L24/20 ,  H01L24/82 ,  H01L2224/06151 ,  H01L2224/221 ,  H01L2224/224 ,  H01L2224/8234 ,  H01L2924/1431 ,  H01L2924/1438

Abstract: According to one embodiment, a semiconductor device includes a first chip, and a second chip bonded to the first chip. The first chip includes: a substrate; a transistor provided on the substrate; a plurality of first wirings provided above the transistor; and a plurality of first pads provided above the first wirings. The second chip includes: a plurality of second pads coupled to the plurality of first pads, respectively; a plurality of second wirings provided above the second pads; and a memory cell array provided above the second wirings. The first wiring, the first pad, the second pad, and the second wiring are coupled to one another in series to form a first pattern.

公开(公告)号：US11562976B2

公开(公告)日：2023-01-24

申请号：US17190006

申请日：2021-03-02

Applicant: Kioxia Corporation

Inventor： Takahiro Tomimatsu ,  Shinya Arai

IPC: H01L23/535 ,  H01L23/00 ,  H01L25/065 ,  H01L25/18 ,  H01L25/00

Abstract: According to one embodiment, a semiconductor device includes a first substrate; a first insulating film provided on the first substrate; a first plug provided in the first insulating film; a second substrate provided on the first insulating film; and a first wiring including a first portion and a second portion. The first portion is provided in the second substrate and coupled to the first plug, and the second portion is provided on the second substrate and coupled to a bonding pad.

公开(公告)号：US11417679B2

公开(公告)日：2022-08-16

申请号：US17011517

申请日：2020-09-03

Applicant: Kioxia Corporation

Inventor： Shinya Arai

IPC: H01L27/11582 ,  H01L27/11578 ,  H01L29/792 ,  H01L27/11565 ,  H01L23/528 ,  H01L23/532 ,  H01L29/06 ,  H01L29/08 ,  H01L29/45

Abstract: According to one embodiment, a semiconductor memory device includes a substrate; an insulating layer provided on the substrate; a conductive layer provided on the insulating layer; a stacked body provided on the conductive layer and including a plurality of electrode layers and a plurality of insulating layers respectively provided among the plurality of electrode layers; a columnar section piercing through the stacked body to reach the conductive layer and extending in a first direction in which the stacked body is stacked; and a source layer. The columnar section includes a channel body and a charge storage film provided between the channel body and the respective electrode layers. The conductive layer includes a first film having electric conductivity and in contact with the lower end portion of the channel body; and an air gap provided to be covered by the first film.

公开(公告)号：US12207470B2

公开(公告)日：2025-01-21

申请号：US18408864

申请日：2024-01-10

Applicant: Kioxia Corporation

Inventor： Shinya Arai

IPC: H10B43/27 ,  G11C16/14 ,  H01L21/764 ,  H01L29/06 ,  H10B41/27 ,  H10B41/35 ,  H10B41/50 ,  H10B43/35 ,  H10B43/40 ,  H10B43/50 ,  G11C16/04 ,  H01L21/02 ,  H01L21/225 ,  H01L21/311 ,  H01L21/3213 ,  H01L29/167 ,  H10B41/41

Abstract: According to one embodiment, a source layer includes a semiconductor layer including an impurity. A stacked body includes a plurality of electrode layers stacked with an insulator interposed. A gate layer is provided between the source layer and the stacked body. The gate layer is thicker than a thickness of one layer of the electrode layers. A semiconductor body extends in a stacking direction of the stacked body through the stacked body and the gate layer. The semiconductor body further extends in the semiconductor layer where a side wall portion of the semiconductor body contacts the semiconductor layer. The semiconductor body does not contact the electrode layers and the gate layer.

公开(公告)号：US11744075B2

公开(公告)日：2023-08-29

申请号：US17672819

申请日：2022-02-16

Applicant: Kioxia Corporation

Inventor： Yoshiaki Fukuzumi ,  Shinya Arai ,  Masaki Tsuji ,  Hideaki Aochi ,  Hiroyasu Tanaka

IPC: H10B43/27 ,  H01L29/66 ,  H01L29/792 ,  H10B43/10 ,  H10B43/50 ,  H01L29/423

CPC classification number: H10B43/27 ,  H01L29/42344 ,  H01L29/66833 ,  H01L29/7926 ,  H10B43/10 ,  H10B43/50

Abstract: A semiconductor memory device includes a connecting member including a semiconductor material, a first electrode film, a first insulating film, a stacked body and three or more semiconductor pillars. The stacked body includes second electrode films and second insulating films that alternately stacked. The semiconductor pillars are arrayed along two or more directions, extend in a stacking direction, pierce through the stacked body and the first insulating film, and are connected to the connecting member. The device includes a third insulating film provided between the semiconductor pillars and the stacked body and between the connecting member and the first electrode film. A charge storage layer is provided at least between one of the second electrode films and the third insulating film.

公开(公告)号：US11778828B2

公开(公告)日：2023-10-03

申请号：US17848789

申请日：2022-06-24

Applicant: KIOXIA CORPORATION

Inventor： Shinya Arai

IPC: H10B43/27 ,  H01L29/792 ,  H10B43/10 ,  H10B43/20 ,  H01L23/528 ,  H01L23/532 ,  H01L29/06 ,  H01L29/08 ,  H01L29/45

CPC classification number: H10B43/27 ,  H01L23/528 ,  H01L23/53257 ,  H01L23/53271 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/45 ,  H01L29/792 ,  H10B43/10 ,  H10B43/20

Abstract: According to one embodiment, a semiconductor memory device includes a substrate; an insulating layer provided on the substrate; a conductive layer provided on the insulating layer; a stacked body provided on the conductive layer and including a plurality of electrode layers and a plurality of insulating layers respectively provided among the plurality of electrode layers; a columnar section piercing through the stacked body to reach the conductive layer and extending in a first direction in which the stacked body is stacked; and a source layer. The columnar section includes a channel body and a charge storage film provided between the channel body and the respective electrode layers. The conductive layer includes a first film having electric conductivity and in contact with the lower end portion of the channel body; and an air gap provided to be covered by the first film.

公开(公告)号：US11758726B2

公开(公告)日：2023-09-12

申请号：US17206763

申请日：2021-03-19

Applicant: Kioxia Corporation

Inventor： Shinya Arai

IPC: H01L21/28 ,  H10B43/27 ,  G11C16/04 ,  H01L49/02 ,  H10B43/30 ,  G11C16/26 ,  H10B41/20 ,  H10B41/23

CPC classification number: H10B43/27 ,  G11C16/0466 ,  G11C16/26 ,  H01L28/00 ,  H01L29/40117 ,  H10B43/30 ,  G11C16/0483 ,  H10B41/20 ,  H10B41/23

Abstract: A semiconductor memory device according to an embodiment comprises: a semiconductor substrate; a stacked body having a plurality of first insulating layers and conductive layers stacked alternately on the semiconductor substrate; a columnar semiconductor layer contacting the semiconductor substrate in the stacked body being provided extending in a stacking direction of the stacked body and including a first portion and a second portion which is provided above the first portion; a memory layer provided on a side surface of the columnar semiconductor layer facing the stacked conductive layers and extending along the columnar semiconductor layer; and a second insulating layer provided between one of the first insulating layer and the conductive layers of the stacked body. The columnar semiconductor layer has a boundary of the first portion and the second portion, the boundary being close to the second insulating layer; and an average value of an outer diameter of the memory layer facing a side surface of the second insulating layer is larger than that of of the memory layer facing a side surface of a lowermost layer of the first insulating layers in the second portion.

公开(公告)号：US11515327B2

公开(公告)日：2022-11-29

申请号：US17200987

申请日：2021-03-15

Applicant: Kioxia Corporation

Inventor： Shinya Arai

IPC: H01L27/11582 ,  H01L27/11573 ,  H01L27/11556 ,  H01L27/11524 ,  H01L27/1157 ,  H01L27/11548 ,  H01L27/11575 ,  H01L21/764 ,  H01L29/06 ,  G11C16/14 ,  G11C16/04 ,  H01L27/11529 ,  H01L21/311 ,  H01L21/3213 ,  H01L21/225 ,  H01L29/167 ,  H01L21/02

Abstract: According to one embodiment, a source layer includes a semiconductor layer including an impurity. A stacked body includes a plurality of electrode layers stacked with an insulator interposed. A gate layer is provided between the source layer and the stacked body. The gate layer is thicker than a thickness of one layer of the electrode layers. A semiconductor body extends in a stacking direction of the stacked body through the stacked body and the gate layer. The semiconductor body further extends in the semiconductor layer where a side wall portion of the semiconductor body contacts the semiconductor layer. The semiconductor body does not contact the electrode layers and the gate layer.

公开(公告)号：US11469217B2

公开(公告)日：2022-10-11

申请号：US17007719

申请日：2020-08-31

Applicant: Kioxia Corporation

Inventor： Shinya Arai

IPC: H01L25/065 ,  H01L23/538 ,  H01L21/50 ,  H01L23/544

Abstract: A semiconductor device includes a first chip and a second chip bonded to the first chip. The first chip includes: a substrate; a logic circuit disposed on the substrate; and a plurality of first dummy pads that are disposed above the logic circuit, are disposed on a first bonding surface where the first chip is bonded to the second chip, the plurality of first dummy pads not being electrically connected to the logic circuit. The second chip includes a plurality of second dummy pads disposed on the plurality of first dummy pads and a memory cell array provided above the plurality of second dummy pads. A coverage of the first dummy pads on the first bonding surface is different between a first region and a second region, the first region separated from a first end side of the first chip, the second region disposed between the first end side and the first region.