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1.发明授权公开(公告)号：US11521678B2
公开(公告)日：2022-12-06
申请号：US17405174
申请日：2021-08-18
Inventor： Donguk Kim , Jun Tae Jang , Dae Hwan Kim , Dong Myoung Kim , Sung Jin Choi
Abstract: The present invention relates to a synapse and synaptic array, and a computing system using the same. The synaptic device according to an exemplary embodiment of the present invention includes a transistor in which a synaptic input signal is applied to any one electrode of source and drain electrodes; and a plurality of two-terminal variable resistance memory devices in which a first electrode is electrically globally connected to a gate electrode of the transistor, wherein a separate memory voltage is applied to a second electrode of each variable resistance memory device to adjust a gate voltage applied to the gate electrode, thereby controlling a synaptic output signal which is output to the other one of the source and drain electrodes.
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公开(公告)号：US12132110B2
公开(公告)日：2024-10-29
申请号：US17462554
申请日：2021-08-31
Inventor： Dae Hwan Kim , Dong Yeon Kang , Jun Tae Jang , Shin Young Park , Hyun Kyu Lee , Sung Jin Choi , Dong Myoung Kim , Wonjung Kim
IPC: H01L29/786 , G06N3/063 , H01L21/02 , H01L29/66 , H01L29/78 , H01L29/788
CPC classification number: H01L29/7841 , G06N3/063 , H01L21/02178 , H01L21/02565 , H01L29/66969 , H01L29/7869 , H01L29/7883
Abstract: Disclosed is a synaptic transistor, including a substrate, an expansion gate electrode disposed to extend in one direction on the substrate, a gate insulating layer including ions, covering the expansion gate electrode, and disposed on the substrate, a channel layer disposed on the gate insulating layer to correspond to one end of the expansion gate electrode, source and drain electrodes spaced apart from each other, covering both ends of the channel layer, and disposed on the gate insulating layer, and a pad electrode disposed on the gate insulating layer to correspond to the other end of the expansion gate electrode.
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