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公开(公告)号：US20200230346A1
公开(公告)日：2020-07-23
申请号：US16525183
申请日：2019-07-29
Inventor： Hyun Sun Mo , Young Rag Do , Dae Jeong Kim , Dae Hwan Kim , Sung Yeon Jang , In Hwan Jung , Dong Myung Kim , Seong Jin Choi , Sanggyu Yim , Hyung Min Kim , Sun Woong Choi , Gu Min Jeong , Seung Min Lee
IPC: A61M21/02
Abstract: Disclosed are an apparatus and a system for managing circadian rhythm. The apparatus includes an illuminance measuring portion which measures a bio illuminance value of external light using a circadian lambda filter which passes the external light along according to a circadian rhythm sensitivity curve and a visual lambda filter which passes the external light along according to a visual sensitivity curve, a controller which outputs a control signal for reinforcing a user's circadian rhythm on the basis of the bio illuminance value, and a circadian rhythm reinforcing portion which emits light of a circadian wavelength band toward the user according to the control signal.
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公开(公告)号：US12132110B2
公开(公告)日：2024-10-29
申请号：US17462554
申请日：2021-08-31
Inventor： Dae Hwan Kim , Dong Yeon Kang , Jun Tae Jang , Shin Young Park , Hyun Kyu Lee , Sung Jin Choi , Dong Myoung Kim , Wonjung Kim
IPC: H01L29/786 , G06N3/063 , H01L21/02 , H01L29/66 , H01L29/78 , H01L29/788
CPC classification number: H01L29/7841 , G06N3/063 , H01L21/02178 , H01L21/02565 , H01L29/66969 , H01L29/7869 , H01L29/7883
Abstract: Disclosed is a synaptic transistor, including a substrate, an expansion gate electrode disposed to extend in one direction on the substrate, a gate insulating layer including ions, covering the expansion gate electrode, and disposed on the substrate, a channel layer disposed on the gate insulating layer to correspond to one end of the expansion gate electrode, source and drain electrodes spaced apart from each other, covering both ends of the channel layer, and disposed on the gate insulating layer, and a pad electrode disposed on the gate insulating layer to correspond to the other end of the expansion gate electrode.
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Patent Agency Ranking
公开(公告)号：US10409126B2
公开(公告)日：2019-09-10
申请号：US13782823
申请日：2013-03-01
Inventor： Jihun Lim , Byung Du Ahn , Gun Hee Kim , Junhyun Park , Jehun Lee , Jaewoo Park , Dae Hwan Kim , Hyunkwang Jung , Jaehyeong Kim
IPC: H01L51/10 , G02F1/1362 , G02F1/1368 , H01L29/417 , H01L29/786
Abstract: A thin film transistor includes a gate electrode, a first insulating layer disposed to cover the gate electrode, a semiconductor layer disposed on the first insulating layer that includes a first side surface portion, a source electrode disposed on the semiconductor layer, and a drain electrode disposed on the first insulating layer that includes a second side surface portion. The first side surface portion makes contact with the second side surface portion.
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公开(公告)号：US11305091B2
公开(公告)日：2022-04-19
申请号：US16525183
申请日：2019-07-29
Inventor： Hyun Sun Mo , Young Rag Do , Dae Jeong Kim , Dae Hwan Kim , Sung Yeon Jang , In Hwan Jung , Dong Myung Kim , Seong Jin Choi , Sanggyu Yim , Hyung Min Kim , Sun Woong Choi , Gu Min Jeong , Seung Min Lee
Abstract: Disclosed are an apparatus and a system for managing circadian rhythm. The apparatus includes an illuminance measuring portion which measures a bio illuminance value of external light using a circadian lambda filter which passes the external light along according to a circadian rhythm sensitivity curve and a visual lambda filter which passes the external light along according to a visual sensitivity curve, a controller which outputs a control signal for reinforcing a user's circadian rhythm on the basis of the bio illuminance value, and a circadian rhythm reinforcing portion which emits light of a circadian wavelength band toward the user according to the control signal.
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公开(公告)号：US09257563B2
公开(公告)日：2016-02-09
申请号：US13798811
申请日：2013-03-13
Inventor： Byung Du Ahn , Jung Hwa Kim , Ji Hun Lim , Je Hun Lee , Dae Hwan Kim , Hyun Kwang Jung
IPC: H01L29/10 , H01L29/786 , H01L29/66 , H01L33/38 , H01L29/417
CPC classification number: H01L29/7869 , H01L29/41733 , H01L29/66969 , H01L29/78693 , H01L33/387
Abstract: A thin film transistor array panel includes a substrate, a gate electrode on the substrate, a gate insulating layer on the gate electrode, a semiconductor layer on the gate insulating layer, a source electrode and a drain electrode on the semiconductor layer and facing each other, a floating metal layer between the source electrode and the drain electrode, and a passivation layer covering the source electrode, the drain electrode, and the floating metal layer. The floating metal layer is electrically floating.
Abstract translation: 薄膜晶体管阵列面板包括基板，基板上的栅极电极，栅电极上的栅极绝缘层，栅极绝缘层上的半导体层，半导体层上的源电极和漏电极，并面对彼此 ，源电极和漏电极之间的浮动金属层，以及覆盖源电极，漏电极和浮置金属层的钝化层。 浮动金属层电浮动。
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公开(公告)号：US09508857B2
公开(公告)日：2016-11-29
申请号：US14635732
申请日：2015-03-02
Inventor： Byung Du Ahn , Ji Hun Lim , Jun Hyung Lim , Dae Hwan Kim , Jae Hyeong Kim , Je Hun Lee , Hyun Kwang Jung
IPC: H01L29/786 , H01L27/12 , H01L21/28
CPC classification number: H01L29/78606 , H01L21/28 , H01L27/124 , H01L29/786 , H01L29/78678 , H01L29/7869 , H01L29/78696
Abstract: A thin film transistor display panel a includes a transparent substrate; a gate electrode positioned on the substrate; a gate insulating layer positioned on the gate electrode; a semiconductor layer positioned on the gate insulating layer and including a channel region; a source electrode and a drain electrode positioned on the semiconductor layer and facing each other; and a passivation layer configured to cover the source electrode, the drain electrode, and the semiconductor layer, wherein the semiconductor layer includes a relatively thick first portion between the source electrode and the gate electrode and a relatively thinner second portion between the drain electrode and the gate electrode overlap, the relatively thick first portion being sufficiently thick to substantially reduce a charge trapping phenomenon that may otherwise occur at a gate electrode to gate dielectric interface if the first portion were as thin as the second portion.
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7.发明授权公开(公告)号：US11521678B2
公开(公告)日：2022-12-06
申请号：US17405174
申请日：2021-08-18
Inventor： Donguk Kim , Jun Tae Jang , Dae Hwan Kim , Dong Myoung Kim , Sung Jin Choi
Abstract: The present invention relates to a synapse and synaptic array, and a computing system using the same. The synaptic device according to an exemplary embodiment of the present invention includes a transistor in which a synaptic input signal is applied to any one electrode of source and drain electrodes; and a plurality of two-terminal variable resistance memory devices in which a first electrode is electrically globally connected to a gate electrode of the transistor, wherein a separate memory voltage is applied to a second electrode of each variable resistance memory device to adjust a gate voltage applied to the gate electrode, thereby controlling a synaptic output signal which is output to the other one of the source and drain electrodes.
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