公开(公告)号：US12210960B2

公开(公告)日：2025-01-28

申请号：US17205790

申请日：2021-03-18

Applicant: KOREA INSTITUTE OF SCIENCE AND TECHNOLOGY

Inventor： Joon Young Kwak ,  Suyoun Lee ,  Inho Kim ,  Jong-Keuk Park ,  Kyeong Seok Lee ,  Jaewook Kim ,  Jongkil Park ,  YeonJoo Jeong ,  Gyuweon Hwang

IPC: G06N3/063 ,  G11C16/04 ,  G11C16/10 ,  H01L29/792

Abstract: Embodiments of inventive concepts relate to a neuromorphic circuit including a flash memory-based spike regulator capable of generating a stable spike signal with a small number of devices. The neuromorphic circuit may generate a simple and stable spike signal using a flash memory-based spike regulator. Therefore, it is possible to implement a semiconductor neuromorphic circuit at low power and low cost by using the spike regulator of the present invention. Example embodiments of inventive concepts provide a neuromorphic circuit comprising a control signal generator for generating a control signal for generating a pulse signal; and a spike regulator for generating a spike signal in response to the control signal. Wherein the spike regulator comprises a first transistor for switching an input signal transmitted to one terminal to the other terminal in response to the control signal; and a first flash memory type transistor having a drain terminal connected to the other terminal of the first transistor and transferring the switched input signal to a source terminal as a spike signal.

公开(公告)号：US11800705B2

公开(公告)日：2023-10-24

申请号：US17538747

申请日：2021-11-30

Applicant: KOREA INSTITUTE OF SCIENCE AND TECHNOLOGY

Inventor： Joon Young Kwak ,  Eunpyo Park ,  Suyoun Lee ,  Inho Kim ,  Jong-Keuk Park ,  Jaewook Kim ,  Jongkil Park ,  YeonJoo Jeong

IPC: H01L29/788 ,  H01L29/43 ,  H01L29/423 ,  H10B41/30 ,  H01L29/66

CPC classification number: H10B41/30 ,  H01L29/42324 ,  H01L29/437 ,  H01L29/66825 ,  H01L29/788

Abstract: A flash memory device is provided. The flash memory device is disposed on a substrate, a channel layer made of a two-dimensional material, sources and drains disposed at both ends of the channel layer, a tunneling insulating layer having a first dielectric constant and a tunneling insulating layer disposed on the channel layer, a floating gate made of a two-dimensional material, a blocking insulating layer disposed on the floating gate and having a second dielectric constant greater than the first dielectric constant, and an upper gate disposed on the blocking insulating layer.