公开(公告)号：US11544541B2

公开(公告)日：2023-01-03

申请号：US16526537

申请日：2019-07-30

Applicant: KOREA INSTITUTE OF SCIENCE AND TECHNOLOGY

Inventor： Suyoun Lee ,  Joon Young Kwak ,  Hyunsu Ju ,  Byung-Ki Cheong

IPC: G06N3/063 ,  G06N3/04

Abstract: An artificial neuron device according to an embodiment of the present disclosure includes a first resistor connected between an input terminal and a first node; a capacitor connected between the first node and a ground terminal; a threshold switch connected between the first node and a second node; and a second resistor connected between the second node and the ground terminal, wherein, when an input voltage of a certain level is applied to the input terminal by time, a membrane potential occurs at the first node and a spike current flows through the second node. According to present disclosure, the artificial neuron device expresses the Integrate-and-Fire function, the rate coding ability, the SFA characteristics, and the chaotic activity of the biological neuron, and therefore may be widely used for the artificial neuron network device, the large-scale brain-inspired computing system, and the artificial intelligence (AI) system.

公开(公告)号：US11431291B1

公开(公告)日：2022-08-30

申请号：US17467457

申请日：2021-09-07

Applicant: KOREA INSTITUTE OF SCIENCE AND TECHNOLOGY

Inventor： Suyoun Lee ,  Seon Jeong Kim ,  Jong-Keuk Park ,  Inho Kim ,  Kyeong Seok Lee ,  Gyu Weon Hwang ,  Joon Young Kwak ,  Jaewook Kim ,  Yeonjoo Jeong ,  Jongkil Park

IPC: H03B5/24 ,  H01L45/00 ,  H03K17/96

Abstract: A nano-oscillator device includes a switching element configured to be switched to an ON state at a threshold voltage or above and switched to an OFF state below a holding voltage; and a load element connected to the switching element in series. In the nano-oscillator device, vibration characteristics are implemented by using a switching element and a load element connected thereto in series. Also, the oscillation frequency of the output waveform of the oscillator may be adjusted in real time according to a gate voltage by using a field effect transistor serving as a load element. Using a synchronization characteristic in which the oscillation frequency and phase are locked with respect to an external input, it is possible to implement a computing system based on a network in which a plurality of oscillator devices are coupled.

公开(公告)号：US12050992B2

公开(公告)日：2024-07-30

申请号：US16971917

申请日：2019-12-31

Applicant: SEOUL NATIONAL UNIVERSITY R&DB FOUNDATION ,  KOREA INSTITUTE OF SCIENCE AND TECHNOLOGY

Inventor： Ki Young Choi ,  Jae Hyun Kim ,  Chae Un Lee ,  Joonyeon Chang ,  Joon Young Kwak ,  Jaewook Kim

IPC: G06N3/08 ,  G06F17/18 ,  G06N3/048 ,  G06N3/065

CPC classification number: G06N3/08 ,  G06F17/18 ,  G06N3/048 ,  G06N3/065

Abstract: An embodiment of the present disclosure discloses a method of process variation compensating through activation value adjustment of an analog binarized neural network circuit that may recover a decrease in recognition rate performance up to an almost perfect level, even if a binarized neural network is implemented as an analog circuit such that recognition rate performance is decreased due to process variation.

公开(公告)号：US12210960B2

公开(公告)日：2025-01-28

申请号：US17205790

申请日：2021-03-18

Applicant: KOREA INSTITUTE OF SCIENCE AND TECHNOLOGY

Inventor： Joon Young Kwak ,  Suyoun Lee ,  Inho Kim ,  Jong-Keuk Park ,  Kyeong Seok Lee ,  Jaewook Kim ,  Jongkil Park ,  YeonJoo Jeong ,  Gyuweon Hwang

IPC: G06N3/063 ,  G11C16/04 ,  G11C16/10 ,  H01L29/792

Abstract: Embodiments of inventive concepts relate to a neuromorphic circuit including a flash memory-based spike regulator capable of generating a stable spike signal with a small number of devices. The neuromorphic circuit may generate a simple and stable spike signal using a flash memory-based spike regulator. Therefore, it is possible to implement a semiconductor neuromorphic circuit at low power and low cost by using the spike regulator of the present invention. Example embodiments of inventive concepts provide a neuromorphic circuit comprising a control signal generator for generating a control signal for generating a pulse signal; and a spike regulator for generating a spike signal in response to the control signal. Wherein the spike regulator comprises a first transistor for switching an input signal transmitted to one terminal to the other terminal in response to the control signal; and a first flash memory type transistor having a drain terminal connected to the other terminal of the first transistor and transferring the switched input signal to a source terminal as a spike signal.

公开(公告)号：US11800705B2

公开(公告)日：2023-10-24

申请号：US17538747

申请日：2021-11-30

Applicant: KOREA INSTITUTE OF SCIENCE AND TECHNOLOGY

Inventor： Joon Young Kwak ,  Eunpyo Park ,  Suyoun Lee ,  Inho Kim ,  Jong-Keuk Park ,  Jaewook Kim ,  Jongkil Park ,  YeonJoo Jeong

IPC: H01L29/788 ,  H01L29/43 ,  H01L29/423 ,  H10B41/30 ,  H01L29/66

CPC classification number: H10B41/30 ,  H01L29/42324 ,  H01L29/437 ,  H01L29/66825 ,  H01L29/788

Abstract: A flash memory device is provided. The flash memory device is disposed on a substrate, a channel layer made of a two-dimensional material, sources and drains disposed at both ends of the channel layer, a tunneling insulating layer having a first dielectric constant and a tunneling insulating layer disposed on the channel layer, a floating gate made of a two-dimensional material, a blocking insulating layer disposed on the floating gate and having a second dielectric constant greater than the first dielectric constant, and an upper gate disposed on the blocking insulating layer.