公开(公告)号：US20140187029A1

公开(公告)日：2014-07-03

申请号：US14200002

申请日：2014-03-06

申请人： KWANG SOO SEOL ,  SEONG SOON CHO ,  BYUNGJOO GO ,  HONGSOO KIM

发明人： KWANG SOO SEOL ,  SEONG SOON CHO ,  BYUNGJOO GO ,  HONGSOO KIM

IPC分类号： G11C5/06 ,  H01L21/768

CPC分类号： H01L21/76877 ,  H01L27/11519 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/11582 ,  H01L29/42332 ,  H01L29/66825 ,  H01L29/7889 ,  H01L29/7926

摘要： A method of fabricating a semiconductor device, comprising: forming a plurality of memory cell strings; coupling an interconnection to at least two of the memory cell strings; and coupling a bitline to the interconnection. The interconnection includes a body extending along a first direction and a protrusion protruding from the body along a second direction.

摘要翻译： 一种制造半导体器件的方法，包括：形成多个存储单元串; 将互连耦合到所述存储单元串中的至少两个; 并将位线耦合到互连。 互连包括沿着第一方向延伸的主体和沿着第二方向从主体突出的突起。

公开(公告)号：US20160343703A1

公开(公告)日：2016-11-24

申请号：US15002679

申请日：2016-01-21

申请人： BYUNGJOO GO ,  HONGSOO KIM

发明人： BYUNGJOO GO ,  HONGSOO KIM

IPC分类号： H01L27/088 ,  H01L27/02 ,  H01L29/417 ,  H01L23/528 ,  H01L29/423

CPC分类号： H01L27/088 ,  H01L21/823475 ,  H01L23/485 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/53295 ,  H01L27/0207

摘要： A semiconductor device includes an active region, a gate pattern on the active region, the active region including a source region at a first side of the gate pattern and a drain region at a second side of the gate pattern, a gate contact pattern on the gate pattern and a drain contact pattern on the drain region, and a gate stud pattern on the gate contact pattern and a drain stud pattern on the drain contact pattern. A distance between a gate contact axis passing through a center portion of the gate contact pattern and a drain contact axis passing through a center portion of the drain contact pattern is different from a distance between a gate stud axis passing through a center portion of the gate stud pattern and a drain stud axis passing through a center portion of the drain stud pattern.

摘要翻译： 半导体器件包括有源区，有源区上的栅极图案，有源区包括在栅极图案的第一侧的源极区域和栅极图案的第二侧处的漏极区域，栅极接触图案 栅极图案和漏极接触图案，以及栅极接触图案上的栅极柱图案和漏极接触图案上的排列螺柱图案。 通过栅极接触图案的中心部分的栅极接触轴线和通过漏极接触图案的中心部分的漏极接触轴之间的距离不同于通过栅极中心部分的栅极柱轴线之间的距离 螺柱图案和穿过排水柱图案的中心部分的排水柱螺栓轴。

公开(公告)号：US20160049422A1

公开(公告)日：2016-02-18

申请号：US14695051

申请日：2015-04-24

申请人： HONGSOO KIM ,  HunKook LEE ,  Jeehoon HWANG

发明人： HONGSOO KIM ,  HunKook LEE ,  Jeehoon HWANG

IPC分类号： H01L27/115

CPC分类号： H01L27/11582 ,  H01L27/11565 ,  H01L27/1157

摘要： A semiconductor device may include an insulating layer provided in one body on a substrate, a first gate electrode and a second gate electrode disposed on the insulating layer, the first and second gate electrodes extending in a first direction parallel to a top surface of the substrate, a first channel structure penetrating the first gate electrode and the insulating layer so as to be connected to the substrate, a second channel structure penetrating the second gate electrode and the insulating layer so as to be connected to the substrate, and a contact penetrating the insulating layer between the first gate electrode and the second gate electrode. The contact may be connected to a common source region formed in the substrate, and the common source region may have a first conductivity type. Further, the first gate electrode and the second gate electrode may be spaced apart from each other in a second direction at the same level from the substrate, wherein the second direction intersects the first direction and is parallel to the top surface of the substrate.

摘要翻译： 半导体器件可以包括设置在基板上的一个主体中的绝缘层，设置在绝缘层上的第一栅电极和第二栅电极，第一和第二栅电极沿平行于基板顶表面的第一方向延伸 贯穿第一栅极电极和绝缘层以连接到基板的第一通道结构，穿过第二栅极电极和绝缘层的第二通道结构以连接到基板，以及穿过该基板的触点 第一栅极电极和第二栅极电极之间的绝缘层。 接触可以连接到形成在基板中的公共源极区域，并且公共源极区域可以具有第一导电类型。 此外，第一栅极电极和第二栅极电极可以在与基板相同的第二方向上彼此间隔开，其中第二方向与第一方向相交并且平行于基板的顶表面。

公开(公告)号：US20150035065A1

公开(公告)日：2015-02-05

申请号：US14295333

申请日：2014-06-04

申请人： Jong-Kook PARK ,  HONGSOO KIM ,  Won-Chul JANG

发明人： Jong-Kook PARK ,  HONGSOO KIM ,  Won-Chul JANG

IPC分类号： H01L23/50 ,  H01L27/06

CPC分类号： H01L27/105 ,  H01L23/485 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device includes a substrate with an active region defined by a device isolation layer. A word line extends over the active region in a first direction, and a plurality of interconnections extends over the word line in a second direction perpendicular to the first direction. A contact pad is disposed between and spaced apart from the word line and the plurality of interconnections, extending in the first direction to overlap the plurality of interconnections and the active region when viewed from a plan view. A lower contact plug electrically connects the contact pad to the active region. An upper contact plug electrically connects the contact pad to one of the plurality of interconnections.

摘要翻译： 半导体器件包括具有由器件隔离层限定的有源区的衬底。 字线在第一方向上在有源区域上延伸，并且多个互连在垂直于第一方向的第二方向上在字线上延伸。 接触垫设置在字线和多个互连之间并与之隔开的多个互连，当从平面图观察时，沿第一方向延伸以与多个互连和有源区重叠。 下接触插头将接触垫电连接到有源区域。 上接触插头将接触垫电连接到多个互连中的一个。