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公开(公告)号：US20200259464A1
公开(公告)日：2020-08-13
申请号：US16535175
申请日：2019-08-08
发明人： Toshiki Seshita , Yasuhiko Kuriyama
摘要： Circuitry includes an amplifier circuit having a first transistor, an inductor, and a second transistor, and a distortion compensation circuit having a third transistor, a forth transistor, and a first capacitor. The first transistor is applied input signal. The inductor is connected to a source of the first transistor and grounded on another side. The second transistor has a source connected to a drain of the first transistor, a grounded gate and a drain connected to a power supply, and outputs an amplified signal. The third transistor has a drain and a gate connected to the drain, and is connected to the power supply on the drain. The fourth transistor has a drain and a gate connected to a source of the third transistor, and is grounded on a source. The first capacitor connects nodes between the drain of the first transistor and the source of the third transistor.
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公开(公告)号：US10033332B2
公开(公告)日：2018-07-24
申请号：US15444242
申请日：2017-02-27
发明人： Toshiki Seshita , Yasuhiko Kuriyama
摘要： According to an embodiment, a high-frequency semiconductor amplifier circuit includes an input terminal and an output terminal. A gate of a first transistor is connected to the input terminal. A drain of the first transistor is connected to the output terminal. A second transistor is connected between a source of the first transistor and a reference potential terminal. A bias generation circuit has an input control signal terminal, a bias voltage terminal connected to the gate of the first transistor, a control voltage terminal connected to a gate of the second transistor, and an intermediate voltage terminal connected to the drain of the first transistor. The bias generation circuit supplies a control voltage, a bias voltage, and a first voltage according to the input control signal.
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公开(公告)号：US09954493B2
公开(公告)日：2018-04-24
申请号：US15460879
申请日：2017-03-16
发明人： Toshiki Seshita , Yasuhiko Kuriyama
CPC分类号： H03F1/223 , H03F1/305 , H03F3/195 , H03F2200/294 , H03F2200/451 , H03F2200/453 , H03F2200/489 , H03F2200/555
摘要： A high-frequency semiconductor amplifier circuit includes a first transistor provided on a SOI (Silicon on Insulator) substrate having a grounded source, a second transistor provided on the SOI substrate and cascode-connected to the first transistor, and a bias generation circuit provided on the SOI substrate and generating a gate voltages for the first and second transistors, and a first voltage for a drain of the second transistor. The bias generation circuit sets the gate voltage of the first transistor to a voltage between a second voltage and a third voltage, wherein the gate voltage is smaller than a voltage between a drain-to-source voltage of the first transistor, and wherein the second voltage is a threshold voltage of the first transistor and the third voltage is a gate-to-source voltage at which a second derivative of a square root of the drain current with respect to the gate-to-source voltage becomes a maximum.
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公开(公告)号：US08975947B1
公开(公告)日：2015-03-10
申请号：US14194615
申请日：2014-02-28
发明人： Toshiki Seshita
IPC分类号： H03K17/16
CPC分类号： H03K17/162
摘要： A shunt switch includes first switching elements provided in series between a first node and a second node. Second switching elements are provided in series between the nodes but not in series with the first switching elements. A distortion generation element connected in series with second switching elements generates a distortion which may be used for compensating for a signal distortion at the first node. A distortion changeover element is connected in parallel with the distortion generation element and is configured to have a conductance state that is opposite to the conductance state of the first switching elements, such that the changeover element is conducting when the first switching elements are in an non-conductive state and non-conducting when the first switching elements are in a conducting state.
摘要翻译： 分流开关包括串联设置在第一节点和第二节点之间的第一开关元件。 第二开关元件串联设置在节点之间，但不与第一开关元件串联。 与第二开关元件串联连接的失真产生元件产生可用于补偿第一节点处的信号失真的失真。 失真转换元件与失真产生元件并联连接，并且被配置为具有与第一开关元件的电导状态相反的导通状态，使得当第一开关元件处于非导通状态时，转换元件导通 并且当第一开关元件处于导通状态时不导通。
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公开(公告)号：US08866530B2
公开(公告)日：2014-10-21
申请号：US13920499
申请日：2013-06-18
发明人： Toshiki Seshita
CPC分类号： H03K3/02 , H01L27/1203
摘要： According to one embodiment, a semiconductor device includes an interface, a power supply, a driver, and a switch section. The interface includes a first MOSFET and converts a terminal switch signal of input serial data into parallel data. The first MOSFET is provided on the SOI substrate and has a back gate in a floating state. The power supply includes a second MOSFET and generates an ON potential higher than a potential of a power supply to be supplied to the interface. The second MOSFET is provided on the SOI substrate and has a back gate connected to a source. The driver includes a third MOSFET and outputs a control signal for controlling the ON potential to be in a high level according to the parallel data. The third MOSFET is provided on the SOI substrate and has a back gate connected to a source.
摘要翻译： 根据一个实施例，半导体器件包括接口，电源，驱动器和开关部分。 该接口包括第一个MOSFET，并将输入串行数据的终端开关信号转换为并行数据。 第一个MOSFET被提供在SOI衬底上并且具有处于浮置状态的背栅极。 电源包括第二MOSFET并且产生高于要供应到接口的电源的电位的导通电位。 第二个MOSFET设置在SOI衬底上，并具有连接到源极的背栅极。 驱动器包括第三MOSFET，并且根据并行数据输出用于控制ON电位处于高电平的控制信号。 第三个MOSFET被提供在SOI衬底上并具有连接到源极的背栅极。
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公开(公告)号：US10965256B2
公开(公告)日：2021-03-30
申请号：US16535175
申请日：2019-08-08
发明人： Toshiki Seshita , Yasuhiko Kuriyama
摘要： Circuitry includes an amplifier circuit having a first transistor, an inductor, and a second transistor, and a distortion compensation circuit having a third transistor, a forth transistor, and a first capacitor. The first transistor is applied input signal. The inductor is connected to a source of the first transistor and grounded on another side. The second transistor has a source connected to a drain of the first transistor, a grounded gate and a drain connected to a power supply, and outputs an amplified signal. The third transistor has a drain and a gate connected to the drain, and is connected to the power supply on the drain. The fourth transistor has a drain and a gate connected to a source of the third transistor, and is grounded on a source. The first capacitor connects nodes between the drain of the first transistor and the source of the third transistor.
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公开(公告)号：US20200220503A1
公开(公告)日：2020-07-09
申请号：US16569312
申请日：2019-09-12
发明人： Toshiki Seshita , Yasuhiko Kuriyama
摘要： A low noise amplifier has a first transistor that amplifies a high frequency input signal, a second transistor that further amplifies the amplified signal to generate an output signal, a first inductor connected between the source of the first transistor and a first reference potential node, a third transistor that is connected between the source of the first transistor and the first inductor, a first capacitor and a first resistor connected in series between a drain of the second transistor and an output node of the low noise amplifier, a second resistor and a third resistor connected in series between a gate of the third transistor and a second reference potential node, and a charge pump circuit that sets a potential of a connection node between the second resistor and the third resistor to a potential lower than a potential of the first reference potential node in the second mode.
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公开(公告)号：US10707823B1
公开(公告)日：2020-07-07
申请号：US16535146
申请日：2019-08-08
发明人： Toshiki Seshita , Yasuhiko Kuriyama
摘要： High-frequency amplifier circuitry includes first amplifier circuitry, second amplifier circuitry, and noise figure improving circuitry. The first amplifier circuitry includes a first transistor and a grounded-gate third transistor. The first transistor has a source grounded via a first source inductor and a gate to which an input signal is applied. The third transistor is configured to output from a drain a signal obtained by amplifying a signal outputted from a drain of the first transistor. The second amplifier circuitry includes a same circuit constant as a circuit constant of the first amplifier circuitry and includes a second transistor and a grounded-gate fourth transistor. The noise figure improving circuitry connects the source of the first transistor and the source of the second transistor to each other.
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公开(公告)号：USRE46490E1
公开(公告)日：2017-07-25
申请号：US14801095
申请日：2015-07-16
发明人： Toshiki Seshita
IPC分类号： H03K3/00
CPC分类号： H03K3/02 , H01L27/1203
摘要： According to one embodiment, a semiconductor device includes an interface, a power supply, a driver, and a switch section. The interface includes a first MOSFET and converts a terminal switch signal of input serial data into parallel data. The first MOSFET is provided on the SOI substrate and has a back gate in a floating state. The power supply includes a second MOSFET and generates an ON potential higher than a potential of a power supply to be supplied to the interface. The second MOSFET is provided on the SOI substrate and has a back gate connected to a source. The driver includes a third MOSFET and outputs a control signal for controlling the ON potential to be in a high level according to the parallel data. The third MOSFET is provided on the SOI substrate and has a back gate connected to a source.
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公开(公告)号：US09692410B2
公开(公告)日：2017-06-27
申请号：US14875288
申请日：2015-10-05
发明人： Toshiki Seshita
IPC分类号： H03K17/693
CPC分类号： H03K17/693
摘要： In an embodiment, semiconductor switch includes first switches switching conduction between input-output nodes and a common node. One of the first switches includes a plurality of first transistors connected in series between an input and output node and the common node. Each of the plurality of first transistors includes first gate electrodes, a second gate electrode, a first and second region in a semiconductor layer having a same conduction type. The first gate electrodes extend in parallel in a first direction. The second gate electrode extending in a direction crossing the first direction and is connected to one end of the first gate electrodes. The second region in the semiconductor layer is disposed on a side of the second gate electrode opposite to the first gate electrodes.
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