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    Process for fabricating CMOS Device
    3.
    发明授权
    Process for fabricating CMOS Device 失效
    CMOS器件制造工艺

    公开(公告)号：US5650341A

    公开(公告)日：1997-07-22

    申请号：US720881

    申请日：1996-10-03

    申请人： Ching-Nan Yang ,  Li-Chun Peng

    发明人： Ching-Nan Yang ,  Li-Chun Peng

    IPC分类号： H01L21/8238 ,  H01L21/265

    CPC分类号： H01L21/823842

    摘要： The present invention is a process used for fabricating a CMOS device, which includes (a) forming a first photoresist over the gate conducting layer, (b) define a first gate upon one of the p-type and the n-type MOS regions, (c) executing a first ion implantation in order to form a first lightly doped drain (LDD) on the one of the p-type and the n-type MOS regions, (d) forming a first gate sidewall on the first gate, (e) executing a second ion implantation in order to form a first source and a first drain on the one of the p-type and the n-type MOS regions, (f) forming a second photoresist over the gate conducting layer, (g) eliminating a portion of the second photoresist and another portion of the gate conducting layer in order to define a second gate upon the other one of the p-type and the n-type MOS regions, (h) performing a third ion implantation in order to form a second lightly doped drain (LDD) on the the other portion of the p-type and the n-type MOS regions, (i) selectively forming a specific oxide on the other one of the p-type and the n-type MOS regions, which is not masked by the second gate, (j) removing a portion of the specific oxide in order to form a second gate sidewall on the second gate, (k) executing a fourth ion implantation in order to form a second source and a second drain on the other one of the p-type and the n-type MOS regions, and (l) eliminating a remaining portion of the second photoresist. According to the present invention which can not only reduce the cost and time but also promote the performance of the fabricated CMOS device.

    摘要翻译： 本发明是用于制造CMOS器件的方法，其包括（a）在栅极导电层上形成第一光致抗蚀剂，（b）在p型和n型MOS区之一上限定第一栅极， （c）执行第一离子注入以便在p型和n型MOS区中的一个上形成第一轻掺杂漏极（LDD），（d）在第一栅极上形成第一栅极侧壁（ （e）执行第二离子注入以便在p型和n型MOS区中的一个上形成第一源极和第一漏极，（f）在栅极导电层上形成第二光致抗蚀剂，（g） 消除第二光致抗蚀剂的一部分和栅极导电层的另一部分，以便在p型和n型MOS区中的另一个上限定第二栅极，（h）执行第三离子注入以便 在p型和n型MOS区的另一部分上形成第二轻掺杂漏极（LDD），（i）选择性地f 在第二栅极未被掩蔽的p型和n型MOS区域中的另一个区域上形成特定氧化物，（j）去除特定氧化物的一部分以便形成第二栅极侧壁 第二栅极，（k）执行第四离子注入，以在p型和n型MOS区中的另一个上形成第二源极和第二漏极，以及（l）消除第二栅极的剩余部分 光刻胶。 根据本发明，其不仅可以降低成本和时间，而且可以提高制造的CMOS器件的性能。

    Polyload sram memory cell with low stanby current
    4.
    发明授权
    Polyload sram memory cell with low stanby current 失效
    具有低稳态电流的多载体存储器单元

    公开(公告)号：US5852573A

    公开(公告)日：1998-12-22

    申请号：US946827

    申请日：1997-10-08

    申请人： Ching-Nan Yang ,  Li-Chun Peng

    发明人： Ching-Nan Yang ,  Li-Chun Peng

    IPC分类号： G11C11/412 ,  H01L27/11 ,  G11C11/00

    CPC分类号： H01L27/1112 ,  G11C11/412 ,  H01L27/11

    摘要： An SRAM cell formed on a semiconductor substrate with low standby current is disclosed. The memory cell includes a first inverter, a second inverter cross-coupled to the first inverter to form a storage element, a first load device coupled to the first inverter, a second load device coupled to the second inverter, a first access transistor coupled to an output port of the first inverter, and a second access transistor coupled to an output port of the second inverter. In this memory cell, the first load device is placed over the second inverter with substantial overlapping therebetween, so that resistance of the first load device increases when an input of the second inverter is at a low potential, thereby decreasing a standby current of the first load device. Similarly, the resistance of the second load device increases when an input of the first inverter is at a low potential.

    摘要翻译： 公开了一种形成在低待机电流的半导体衬底上的SRAM单元。 存储单元包括第一反相器，与第一反相器交叉耦合以形成存储元件的第二反相器，耦合到第一反相器的第一负载器件，耦合到第二反相器的第二负载器件，耦合到第二反相器的第一存取晶体管 第一反相器的输出端口和耦合到第二反相器的输出端口的第二存取晶体管。 在该存储单元中，将第一负载装置放置在第二逆变器上，并且在第二逆变器之间具有相当大的重叠，使得当第二反相器的输入处于低电位时第一负载装置的电阻增加，从而降低第一负载装置的待机电流 负载设备 类似地，当第一反相器的输入处于低电位时，第二负载装置的电阻增加。

    Process for manufacturing CMOS device
    5.
    发明授权
    Process for manufacturing CMOS device 失效
    CMOS器件制造工艺

    公开(公告)号：US5747368A

    公开(公告)日：1998-05-05

    申请号：US720762

    申请日：1996-10-03

    申请人： Ching-Nan Yang ,  Li-Chun Peng

    发明人： Ching-Nan Yang ,  Li-Chun Peng

    IPC分类号： H01L21/8238

    CPC分类号： H01L21/823892

    摘要： A process for manufacturing a CMOS device is disclosed. The process includes steps of forming a field oxide over a pad oxide excluding an active area in order to function the field oxide as an isolation layer; forming a gate oxide on the active area; forming a gate conducting layer over the field oxide and the gate oxide; forming a photoresist on the gate conducting layer; removing a portion of the photoresist and executing a first ion implantation in order to regulate a first threshold voltage of the one of the p-type and the n-type MOS regions; selectively forming an oxide on the gate conducting layer on the one of the p-type and the n-type MOS regions; eliminating a remaining portion of the photoresist on the other one of the p-type and the n-type MOS regions and executing a second ion implantation in order to regulate a second threshold voltage of the the other one of the p-type and the n-type MOS regions; and eliminating the oxide on the one of the p-type and the n-type MOS regions and forming gates, sources and drains in the CMOS device by patterning and etching the gate conducting layer.

    摘要翻译： 公开了一种用于制造CMOS器件的工艺。 该方法包括以下步骤：在除活性区域之外的衬垫氧化物上形成场氧化物，以便使场氧化物起隔离层的作用; 在有源区上形成栅极氧化物; 在场氧化物和栅极氧化物上形成栅极导电层; 在栅极导电层上形成光致抗蚀剂; 去除一部分光致抗蚀剂并执行第一离子注入以便调节p型和n型MOS区之一的第一阈值电压; 在p型和n型MOS区中的一个上的栅极导电层上选择性地形成氧化物; 消除在p型和n型MOS区中的另一个上的光致抗蚀剂的剩余部分，并执行第二离子注入，以便调节p型和n型中的另一个的第二阈值电压 型MOS区; 并且消除p型和n型MOS区中的一个上的氧化物，并通过图案化和蚀刻栅极导电层在CMOS器件中形成栅极，源极和漏极。