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    Semiconductor fabrication method suitable for MEMS
    3.
    发明授权
    Semiconductor fabrication method suitable for MEMS 有权
    适用于MEMS的半导体制造方法

    公开(公告)号：US08084361B2

    公开(公告)日：2011-12-27

    申请号：US11755437

    申请日：2007-05-30

    申请人： Tsung-Cheng Huang ,  Hua-Shu Wu ,  Fa-Yuan Chang ,  I-Ching Lin ,  Hsi-Lung Lee ,  Yuan-Hao Chien

    发明人： Tsung-Cheng Huang ,  Hua-Shu Wu ,  Fa-Yuan Chang ,  I-Ching Lin ,  Hsi-Lung Lee ,  Yuan-Hao Chien

    IPC分类号： H01L21/3213

    CPC分类号： B81C1/00634 ,  B81B2201/052

    摘要： A method includes depositing a layer of a sacrificial material in a first region above a substrate. The first region of the substrate is separate from a second region of the substrate, where a corrosion resistant film is to be provided above the second region. The corrosion resistant film is deposited, so that a first portion of the corrosion resistant film is above the sacrificial material in the first region, and a second portion of the corrosion resistant film is above the second region. The first portion of the corrosion resistant film is removed by chemical mechanical polishing. The sacrificial material is removed from the first region using an etching process that selectively etches the sacrificial material, but not the corrosion resistant film.

    摘要翻译： 一种方法包括在基底上方的第一区域中沉积牺牲材料层。 衬底的第一区域与衬底的第二区域分离，其中在第二区域上方设置耐腐蚀膜。 沉积耐腐蚀膜，使得耐腐蚀膜的第一部分在第一区域中的牺牲材料之上，并且耐腐蚀膜的第二部分高于第二区域。 通过化学机械抛光除去耐腐蚀膜的第一部分。 使用选择性蚀刻牺牲材料而不是耐腐蚀膜的蚀刻工艺从第一区域去除牺牲材料。

    SEMICONDUCTOR FABRICATION METHOD SUITABLE FOR MEMS
    4.
    发明申请
    SEMICONDUCTOR FABRICATION METHOD SUITABLE FOR MEMS 有权
    适用于MEMS的半导体制造方法

    公开(公告)号：US20080299769A1

    公开(公告)日：2008-12-04

    申请号：US11755437

    申请日：2007-05-30

    申请人： Tsung-Cheng Huang ,  Hua-Shu Wu ,  Fa-Yuan Chang ,  I-Ching Lin ,  Hsi-Lung Lee ,  Yuan-Hao Chien

    发明人： Tsung-Cheng Huang ,  Hua-Shu Wu ,  Fa-Yuan Chang ,  I-Ching Lin ,  Hsi-Lung Lee ,  Yuan-Hao Chien

    IPC分类号： H01L21/463

    CPC分类号： B81C1/00634 ,  B81B2201/052

    摘要： A method includes depositing a layer of a sacrificial material in a first region above a substrate. The first region of the substrate is separate from a second region of the substrate, where a corrosion resistant film is to be provided above the second region. The corrosion resistant film is deposited, so that a first portion of the corrosion resistant film is above the sacrificial material in the first region, and a second portion of the corrosion resistant film is above the second region. The first portion of the corrosion resistant film is removed by chemical mechanical polishing. The sacrificial material is removed from the first region using an etching process that selectively etches the sacrificial material, but not the corrosion resistant film.

    摘要翻译： 一种方法包括在基底上方的第一区域中沉积牺牲材料层。 衬底的第一区域与衬底的第二区域分离，其中在第二区域上方设置耐腐蚀膜。 沉积耐腐蚀膜，使得耐腐蚀膜的第一部分在第一区域中的牺牲材料之上，并且耐腐蚀膜的第二部分高于第二区域。 通过化学机械抛光除去耐腐蚀膜的第一部分。 使用选择性蚀刻牺牲材料而不是耐腐蚀膜的蚀刻工艺从第一区域去除牺牲材料。

    Split gate flash memory
    5.
    发明授权
    Split gate flash memory 失效
    分闸门闪存

    公开(公告)号：US07208796B2

    公开(公告)日：2007-04-24

    申请号：US11163223

    申请日：2005-10-11

    申请人： Ko-Hsing Chang ,  Wu-Tsung Chung ,  Tsung-Cheng Huang

    发明人： Ko-Hsing Chang ,  Wu-Tsung Chung ,  Tsung-Cheng Huang

    IPC分类号： H01L29/788

    CPC分类号： H01L27/11521 ,  H01L21/28273 ,  H01L27/115 ,  H01L29/42324 ,  H01L29/7885

    摘要： A split gate flash memory is provided. Trenches are formed in the substrate to define active layers. The device isolation layers are formed in the trenches. The surface of the device isolation layers is lower than the surface of the active layers. The stacked gate structures each including a tunneling dielectric layer, a floating gate and a cap layer are formed on the active layers. The inter-gate dielectric layers are formed on the sidewalls of the stacked gate structures. The select gates are formed on one side of the stacked gate structure and across the active layer. The select gate dielectric layers are formed between the select gates and the active layers. The source regions are formed in the active layers on the other side of the stacked gate structures. The drain regions are formed in the active layers on one side of the select gates.

    摘要翻译： 提供了分闸门闪存。 在衬底中形成沟槽以限定活性层。 器件隔离层形成在沟槽中。 器件隔离层的表面低于有源层的表面。 在有源层上形成各自包括隧道电介质层，浮栅和覆盖层的层叠栅极结构。 栅极间电介质层形成在堆叠的栅极结构的侧壁上。 选择栅极形成在层叠的栅极结构的一侧并跨越有源层。 选择栅极电介质层形成在选择栅极和有源层之间。 源极区域形成在堆叠栅极结构的另一侧上的有源层中。 漏极区域形成在选择栅极一侧的有源层中。

    One time programmable memory and the manufacturing method thereof
    6.
    发明授权
    One time programmable memory and the manufacturing method thereof 有权
    一次性可编程存储器及其制造方法

    公开(公告)号：US07491998B2

    公开(公告)日：2009-02-17

    申请号：US11536693

    申请日：2006-09-29

    申请人： Ko-Hsing Chang ,  Tsung-Cheng Huang ,  Yan-Hung Huang

    发明人： Ko-Hsing Chang ,  Tsung-Cheng Huang ,  Yan-Hung Huang

    IPC分类号： H01L29/76

    CPC分类号： H01L29/7883 ,  G11C16/0433 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11558

    摘要： A one time programmable memory including a substrate, a plurality of isolation structures, a first transistor, and a second transistor is provided. The isolation structures are disposed in the substrate for defining an active area. A recess is formed on each of the isolation structures so that the top surface of the isolation structure is lower than that of the substrate. The first transistor is disposed on the active area of the substrate and is extended to the sidewall of the recess. The gate of the first transistor is a select gate. The second transistor is disposed on the active area of the substrate and is connected to the first transistor in series. The gate of the second transistor is a floating gate which is disposed across the substrate between the isolation structures in blocks and is extended to the sidewall of the recess.

    摘要翻译： 提供一种包括衬底，多个隔离结构，第一晶体管和第二晶体管的可编程存储器。 隔离结构设置在基板中以限定有效区域。 在每个隔离结构上形成凹部，使得隔离结构的顶表面低于衬底的顶表面。 第一晶体管设置在衬底的有源区上并延伸到凹槽的侧壁。 第一晶体管的栅极是选择栅极。 第二晶体管设置在衬底的有源区上，并串联连接到第一晶体管。 第二晶体管的栅极是浮动栅极，其在块之间的隔离结构之间横跨衬底设置并且延伸到凹部的侧壁。

    ONE TIME PROGRAMMABLE MEMORY AND THE MANUFACTURING METHOD THEREOF
    7.
    发明申请
    ONE TIME PROGRAMMABLE MEMORY AND THE MANUFACTURING METHOD THEREOF 有权
    一次性可编程存储器及其制造方法

    公开(公告)号：US20070221980A1

    公开(公告)日：2007-09-27

    申请号：US11536693

    申请日：2006-09-29

    申请人： Ko-Hsing Chang ,  Tsung-Cheng Huang ,  Yan-Hung Huang

    发明人： Ko-Hsing Chang ,  Tsung-Cheng Huang ,  Yan-Hung Huang

    IPC分类号： H01L29/76

    CPC分类号： H01L29/7883 ,  G11C16/0433 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11558

    摘要： A one time programmable memory including a substrate, a plurality of isolation structures, a first transistor, and a second transistor is provided. The isolation structures are disposed in the substrate for defining an active area. A recess is formed on each of the isolation structures so that the top surface of the isolation structure is lower than that of the substrate. The first transistor is disposed on the active area of the substrate and is extended to the sidewall of the recess. The gate of the first transistor is a select gate. The second transistor is disposed on the active area of the substrate and is connected to the first transistor in series. The gate of the second transistor is a floating gate which is disposed across the substrate between the isolation structures in blocks and is extended to the sidewall of the recess.

    摘要翻译： 提供一种包括衬底，多个隔离结构，第一晶体管和第二晶体管的可编程存储器。 隔离结构设置在基板中以限定有效区域。 在每个隔离结构上形成凹部，使得隔离结构的顶表面低于衬底的顶表面。 第一晶体管设置在衬底的有源区上并延伸到凹槽的侧壁。 第一晶体管的栅极是选择栅极。 第二晶体管设置在衬底的有源区上，并串联连接到第一晶体管。 第二晶体管的栅极是浮动栅极，其在块之间的隔离结构之间横跨衬底设置并且延伸到凹部的侧壁。

    SPLIT GATE FLASH MEMORY AND MANUFACTURING METHOD THEREOF
    8.
    发明申请
    SPLIT GATE FLASH MEMORY AND MANUFACTURING METHOD THEREOF 失效
    分闸门闪存及其制造方法

    公开(公告)号：US20060208307A1

    公开(公告)日：2006-09-21

    申请号：US11163223

    申请日：2005-10-11

    申请人： Ko-Hsing Chang ,  Wu-Tsung Chung ,  Tsung-Cheng Huang

    发明人： Ko-Hsing Chang ,  Wu-Tsung Chung ,  Tsung-Cheng Huang

    IPC分类号： H01L29/788 ,  H01L21/336

    CPC分类号： H01L27/11521 ,  H01L21/28273 ,  H01L27/115 ,  H01L29/42324 ,  H01L29/7885

    摘要： A split gate flash memory is provided. Trenches are formed in the substrate to define active layers. The device isolation layers are formed in the trenches. The surface of the device isolation layers is lower than the surface of the active layers. The stacked gate structures each including a tunneling dielectric layer, a floating gate and a cap layer are formed on the active layers. The inter-gate dielectric layers are formed on the sidewalls of the stacked gate structures. The select gates are formed on one side of the stacked gate structure and across the active layer. The select gate dielectric layers are formed between the select gates and the active layers. The source regions are formed in the active layers on the other side of the stacked gate structures. The drain regions are formed in the active layers on one side of the select gates.

    摘要翻译： 提供了分闸门闪存。 在衬底中形成沟槽以限定活性层。 器件隔离层形成在沟槽中。 器件隔离层的表面低于有源层的表面。 在有源层上形成各自包括隧道电介质层，浮栅和覆盖层的层叠栅极结构。 栅极间电介质层形成在堆叠的栅极结构的侧壁上。 选择栅极形成在层叠的栅极结构的一侧并跨越有源层。 选择栅极电介质层形成在选择栅极和有源层之间。 源极区域形成在堆叠栅极结构的另一侧上的有源层中。 漏极区域形成在选择栅极一侧的有源层中。

    Non-volatile memory
    9.
    发明授权
    Non-volatile memory 有权
    非易失性存储器

    公开(公告)号：US07446370B2

    公开(公告)日：2008-11-04

    申请号：US11308667

    申请日：2006-04-20

    申请人： Ko-Hsing Chang ,  Tsung-Cheng Huang ,  Yan-Hung Huang

    发明人： Ko-Hsing Chang ,  Tsung-Cheng Huang ,  Yan-Hung Huang

    IPC分类号： H01L29/788

    CPC分类号： H01L27/115 ,  H01L27/11519 ,  H01L27/11521

    摘要： A non-volatile memory is provided, including a substrate, a control gate, a floating gate, and a select gate. A source region and a drain region are disposed in the substrate. The control gate is disposed on the substrate between the source region and the drain region. The floating gate is disposed between the control gate and the substrate. The cross-section of the floating gate presents, for example, an L-shape and the floating gate includes a central region which is perpendicular to the substrate and a lateral region which is parallel to the substrate. The central region is adjacent to the source region. The select gate is disposed on the sidewall of the control gate and the lateral region of the floating gate, and is adjacent to the drain region. Besides, the present invention further includes a method of manufacturing the above non-volatile memory.

    摘要翻译： 提供了一种非易失性存储器，包括基板，控制栅极，浮动栅极和选择栅极。 源极区域和漏极区域设置在衬底中。 控制栅极设置在源极区域和漏极区域之间的衬底上。 浮栅设置在控制栅极和衬底之间。 浮动栅极的横截面呈现例如L形，并且浮动栅极包括垂直于衬底的中心区域和平行于衬底的横向区域。 中心区域与源区域相邻。 选择栅极设置在控制栅极的侧壁和浮置栅极的横向区域上，并且与漏极区域相邻。 此外，本发明还包括制造上述非易失性存储器的方法。

    NON-VOLATILE MEMORY AND MANUFACTURING METHOD THEREOF
    10.
    发明申请
    NON-VOLATILE MEMORY AND MANUFACTURING METHOD THEREOF 有权
    非易失性存储器及其制造方法

    公开(公告)号：US20070262368A1

    公开(公告)日：2007-11-15

    申请号：US11308667

    申请日：2006-04-20

    申请人： Ko-Hsing Chang ,  Tsung-Cheng Huang ,  Yan-Hung Huang

    发明人： Ko-Hsing Chang ,  Tsung-Cheng Huang ,  Yan-Hung Huang

    IPC分类号： H01L29/76

    CPC分类号： H01L27/115 ,  H01L27/11519 ,  H01L27/11521

    摘要： A non-volatile memory is provided, including a substrate, a control gate, a floating gate, and a select gate. A source region and a drain region are disposed in the substrate. The control gate is disposed on the substrate between the source region and the drain region. The floating gate is disposed between the control gate and the substrate. The cross-section of the floating gate presents, for example, an L-shape and the floating gate includes a central region which is perpendicular to the substrate and a lateral region which is parallel to the substrate. The central region is adjacent to the source region. The select gate is disposed on the sidewall of the control gate and the lateral region of the floating gate, and is adjacent to the drain region. Besides, the present invention further includes a method of manufacturing the above non-volatile memory.

    摘要翻译： 提供了一种非易失性存储器，包括基板，控制栅极，浮动栅极和选择栅极。 源极区域和漏极区域设置在衬底中。 控制栅极设置在源极区域和漏极区域之间的衬底上。 浮栅设置在控制栅极和衬底之间。 浮动栅极的横截面呈现例如L形，并且浮动栅极包括垂直于衬底的中心区域和平行于衬底的横向区域。 中心区域与源区域相邻。 选择栅极设置在控制栅极的侧壁和浮置栅极的横向区域上，并且与漏极区域相邻。 此外，本发明还包括制造上述非易失性存储器的方法。