公开(公告)号：US20100244714A1

公开(公告)日：2010-09-30

申请号：US12742103

申请日：2007-11-13

申请人： Kamel Abouda ,  Murielle Delage ,  Erwan Hemon ,  Pierre Turpin

发明人： Kamel Abouda ,  Murielle Delage ,  Erwan Hemon ,  Pierre Turpin

IPC分类号： H05B37/02 ,  H03H11/26

CPC分类号： H03K17/166 ,  H03K17/145 ,  H03K2217/0027

摘要： A circuit for improving the control of a change in state of a signal in an electronic device between a first state and a second state, wherein a first change in state occurs when the state changes from the second state to the first state and a second change in state occurs when the state changes from the first state to the second state and wherein the first and second changes in state have associated therewith a first and a second time delay over which the or each change in state occurs, characterized in that said circuit comprises a determining unit for measuring the first time delay and a calculator for calculating a common delay to replace one or more of the first and second delays to thereby improve the control of the change in state of the signal

摘要翻译： 一种用于改善在第一状态和第二状态之间对电子设备中的信号状态变化的控制的电路，其中当状态从第二状态变为第一状态时发生第一状态变化，并且第二变化 当状态从第一状态改变到第二状态时，发生状态，并且其中第一和第二状态改变已经与第一和第二时间延迟相关联，其中状态或每种状态发生变化，其特征在于，所述电路包括 用于测量第一时间延迟的确定单元和用于计算用于替换第一和第二延迟中的一个或多个的公共延迟的计算器，从而改善信号状态变化的控制

公开(公告)号：US08384313B2

公开(公告)日：2013-02-26

申请号：US12742103

申请日：2007-11-13

申请人： Kamel Abouda ,  Murielle Delage ,  Erwan Hemon ,  Pierre Turpin

发明人： Kamel Abouda ,  Murielle Delage ,  Erwan Hemon ,  Pierre Turpin

IPC分类号： H05B37/02

CPC分类号： H03K17/166 ,  H03K17/145 ,  H03K2217/0027

摘要： A circuit for improving the control of a change in state of a signal in an electronic device between a first state and a second state, wherein a first change in state occurs when the state changes from the second state to the first state and a second change in state occurs when the state changes from the first state to the second state and wherein the first and second changes in state have associated therewith a first and a second time delay over which each change in state occurs, characterized in that said circuit comprises a determining unit for measuring the first time delay and a calculator for calculating a common delay to replace one or more of the first and second delays to thereby improve the control of the change in state of the signal.

摘要翻译： 一种用于改善在第一状态和第二状态之间对电子设备中的信号状态变化的控制的电路，其中当状态从第二状态变为第一状态时发生第一状态变化，并且第二变化 当状态从第一状态改变到第二状态时，发生状态，并且其中状态的第一和第二变化与其相关联地产生每个状态变化的第一和第二时间延迟，其特征在于，所述电路包括确定 用于测量第一时间延迟的单元和用于计算用于替换第一和第二延迟中的一个或多个的公共延迟的计算器，从而改善对信号状态变化的控制。

公开(公告)号：US08598886B2

公开(公告)日：2013-12-03

申请号：US12920600

申请日：2008-03-20

申请人： Kamel Abouda ,  Stephanie Creveau-Boury ,  Murielle Delage ,  Pierre Turpin

发明人： Kamel Abouda ,  Stephanie Creveau-Boury ,  Murielle Delage ,  Pierre Turpin

IPC分类号： G01R31/08

CPC分类号： G01R31/025 ,  G01R31/007 ,  G01R31/024

摘要： Apparatus for detecting faults in the delivery of electrical power to electrical loads, includes a plurality of load electrical connections arranged to deliver electrical power from an electrical power source to each of a plurality of electrical loads, a plurality of electrical switches, each connected to an associated one of the load connections, and a diagnostic device operable to detect a short circuit fault in the apparatus, wherein the diagnostic device is operable to apply a diagnostic procedure to detect a short circuit connection between at least two of the load electrical connections and includes a control logic unit operable to apply to each of the electrical switches in turn a test control signal causing operation of the switch to apply a test electrical signal to each of the load electrical connections in turn; and detector means connected to the load electrical connections and operable, while the test electrical signal is applied in turn to each load electrical connection, to detect whether a corresponding electrical output is produced in response on any of the other load electrical connections. Also described is a method of operation in the apparatus.

摘要翻译： 用于检测向电力负载递送电力中的故障的装置包括多个负载电连接，其被布置为将电力从电源传送到多个电负载中的每一个，多个电开关，每个电连接到 相关联的负载连接之一，以及可操作以检测装置中的短路故障的诊断装置，其中诊断装置可操作以应用诊断程序来检测至少两个负载电连接之间的短路连接，并且包括 控制逻辑单元，可操作以依次向每个电开关施加测试控制信号，使得开关的操作依次对每个负载电连接施加测试电信号; 以及检测器装置，其连接到负载电连接并且可操作，同时将测试电信号依次施加到每个负载电连接，以检测在任何其它负载电连接上是否响应地产生相应的电输出。 还描述了该装置中的操作方法。

公开(公告)号：US09482711B2

公开(公告)日：2016-11-01

申请号：US14094097

申请日：2013-12-02

申请人： Kamel Abouda ,  Stephanie Creveau-Boury ,  Murielle Delage ,  Pierre Turpin

发明人： Kamel Abouda ,  Stephanie Creveau-Boury ,  Murielle Delage ,  Pierre Turpin

IPC分类号： G01R31/08 ,  G01R31/02 ,  G01R31/00

CPC分类号： G01R31/025 ,  G01R31/007 ,  G01R31/024

摘要： A method of and apparatus for fault detection utilizing a diagnostic procedure by a diagnostic device to detect a short circuit between at least two of a plurality of load electrical connections, the diagnostic procedure comprising applying a test electrical signal to each of the load electrical connections in turn and while applying the test electrical signal to a first one of the load electrical connections, detecting whether an electrical output is present, in response, on any other of the load electrical connections, wherein the detecting by the diagnostic device includes applying the test electrical signal to the first one of the load electrical connections in an operational mode of the apparatus when an electrically controlled switch connected to the first one of the load electrical connections is in an off state.

摘要翻译： 一种用于故障检测的方法和装置，利用诊断装置的诊断程序来检测多个负载电连接中的至少两个之间的短路，所述诊断程序包括将测试电信号施加到每个负载电连接中 并且在将所述测试电信号应用于所述负载电连接中的第一负载电连接的同时，检测电输出是否存在于任何另外的所述负载电连接上，其中所述诊断装置的检测包括施加所述测试电气 当连接到第一负载电连接的电控开关处于断开状态时，在装置的操作模式下，向第一负载电连接信号。

公开(公告)号：US20110001486A1

公开(公告)日：2011-01-06

申请号：US12920600

申请日：2008-03-20

申请人： Kamel Abouda ,  Stephanie Creveau-Boury ,  Murielle Delage ,  Pierre Turpin

发明人： Kamel Abouda ,  Stephanie Creveau-Boury ,  Murielle Delage ,  Pierre Turpin

IPC分类号： G01R31/02

CPC分类号： G01R31/025 ,  G01R31/007 ,  G01R31/024

摘要： Apparatus for detecting faults in the delivery of electrical power to electrical loads, includes a plurality of load electrical connections arranged to deliver electrical power from an electrical power source to each of a plurality of electrical loads, a plurality of electrical switches, each connected to an associated one of the load connections, and a diagnostic device operable to detect a short circuit fault in the apparatus, wherein the diagnostic device is operable to apply a diagnostic procedure to detect a short circuit connection between at least two of the load electrical connections and includes a control logic unit operable to apply to each of the electrical switches in turn a test control signal causing operation of the switch to apply a test electrical signal to each of the load electrical connections in turn; and detector means connected to the load electrical connections and operable, whilst the test electrical signal is applied in turn to each load electrical connection, to detect whether a corresponding electrical output is produced in response on any of the other load electrical connections. Also described is a method of operation in the apparatus.

摘要翻译： 用于检测向电力负载递送电力中的故障的装置包括多个负载电连接，其被布置为将电力从电源传送到多个电负载中的每一个，多个电开关，每个电连接到 相关联的负载连接之一，以及可操作以检测装置中的短路故障的诊断装置，其中诊断装置可操作以应用诊断程序来检测至少两个负载电连接之间的短路连接，并且包括 控制逻辑单元，可操作以依次向每个电开关施加测试控制信号，使得开关的操作依次对每个负载电连接施加测试电信号; 以及连接到负载电连接并且可操作的检测器装置，同时将测试电信号依次施加到每个负载电连接，以检测是否响应于任何其它负载电连接而产生相应的电输出。 还描述了该装置中的操作方法。

公开(公告)号：US20100171528A1

公开(公告)日：2010-07-08

申请号：US12294798

申请日：2006-03-27

申请人： Laurent Guillot ,  Kamel Abouda ,  Pierre Turpin

发明人： Laurent Guillot ,  Kamel Abouda ,  Pierre Turpin

IPC分类号： H03K5/19

CPC分类号： G01R29/0273 ,  G06F1/24

摘要： A clock failure detection circuit comprises clock failure detection logic having a clock input providing an input clock signal, a counter and a reference clock input providing a reference clock signal to the counter for counting a number of reference clock cycles. The counter comprises a reset input arranged to receive successive reset pulses generated by at least one clock edge of the input clock signal to reset a counter value of the counter. The counter value before reset is used to identify a clock frequency error. A method of detecting a clock failure is also described. By using a counter value based on the reference clock cycles, and a reset trigger based on a clock edge of the input signal, it is possible to identify a clock frequency error in a much shorter time.

摘要翻译： 时钟故障检测电路包括具有提供输入时钟信号的时钟输入的时钟故障检测逻辑，计数器和向计数器提供参考时钟信号的参考时钟输入，用于对多个参考时钟周期进行计数。 计数器包括复位输入，该复位输入被布置成接收由输入时钟信号的至少一个时钟沿产生的连续复位脉冲，以重置计数器的计数器值。 复位前的计数器值用于识别时钟频率误差。 还描述了一种检测时钟故障的方法。 通过使用基于参考时钟周期的计数器值和基于输入信号的时钟沿的复位触发，可以在更短的时间内识别时钟频率误差。

公开(公告)号：US07924061B2

公开(公告)日：2011-04-12

申请号：US12294798

申请日：2006-03-27

申请人： Laurent Guillot ,  Kamel Abouda ,  Pierre Turpin

发明人： Laurent Guillot ,  Kamel Abouda ,  Pierre Turpin

IPC分类号： H03K5/19

CPC分类号： G01R29/0273 ,  G06F1/24

摘要： A clock failure detection circuit comprises clock failure detection logic having a clock input providing an input clock signal, a counter and a reference clock input providing a reference clock signal to the counter for counting a number of reference clock cycles. The counter comprises a reset input arranged to receive successive reset pulses generated by at least one clock edge of the input clock signal to reset a counter value of the counter. The counter value before reset is used to identify a clock frequency error. A method of detecting a clock failure is also described. By using a counter value based on the reference clock cycles, and a reset trigger based on a clock edge of the input signal, it is possible to identify a clock frequency error in a much shorter time.

摘要翻译： 时钟故障检测电路包括具有提供输入时钟信号的时钟输入的时钟故障检测逻辑，计数器和向计数器提供参考时钟信号的参考时钟输入，用于对多个参考时钟周期进行计数。 计数器包括复位输入，该复位输入被布置成接收由输入时钟信号的至少一个时钟沿产生的连续复位脉冲，以重置计数器的计数器值。 复位前的计数器值用于识别时钟频率误差。 还描述了一种检测时钟故障的方法。 通过使用基于参考时钟周期的计数器值和基于输入信号的时钟沿的复位触发，可以在更短的时间内识别时钟频率误差。

公开(公告)号：US20150188328A1

公开(公告)日：2015-07-02

申请号：US14423481

申请日：2012-09-12

申请人： Kamel Abouda ,  Estelle Huynh ,  Thierry LaPlagne

发明人： Kamel Abouda ,  Estelle Huynh ,  Thierry LaPlagne

IPC分类号： H02J7/00 ,  H02M3/158 ,  F02M51/06

CPC分类号： H02J7/007 ,  F02D41/20 ,  F02D2041/2006 ,  F02D2041/2013 ,  F02D2041/2027 ,  F02D2041/2075 ,  F02M51/06 ,  H02J7/345 ,  H02M1/08 ,  H02M3/155 ,  H02M3/158 ,  H03K17/063 ,  H03K17/162 ,  H03K2217/0081

摘要： A charging circuit for a bootstrap capacitor comprises a P MOSFET having a body diode and an N channel power MOSFET also having a body diode. The drain of the P MOSFET is coupled to the source of the N channel power MOSFET, and the source of the P MOSFET receives current from a vehicle's battery. The gate of the P MOSFET receives a control signal for turning the P MOSFET either on or off and the drain of the N channel power MOSFET is connected to a bootstrap capacitor The P MOSFET's body diode prevents current flow from the battery to the bootstrap capacitor when the P MOSFET is turned off and the N MOSFET's body diode prevents current flow from the bootstrap capacitor to the battery when the N MOSFET is turned off. The use of a power MOSFET device with its low ON resistance ensures that the capacitor is charged to a sufficiently high voltage even under low battery conditions.

摘要翻译： 用于自举电容器的充电电路包括具有体二极管的P MOSFET和还具有体二极管的N沟道功率MOSFET。 P MOSFET的漏极耦合到N沟道功率MOSFET的源极，P MOSFET的源极接收来自车辆电池的电流。 P MOSFET的栅极接收用于使P MOSFET导通或关断的控制信号，并且N沟道功率MOSFET的漏极连接到自举电容器P MOSFET的体二极管防止电流从电池流向自举电容器 当N MOSFET关闭时，P MOSFET关闭，N MOSFET的体二极管防止电流从自举电容流向电池。 使用具有低导通电阻的功率MOSFET器件，即使在低电量条件下也能将电容充电至足够高的电压。

公开(公告)号：US07936200B2

公开(公告)日：2011-05-03

申请号：US12294799

申请日：2007-01-08

申请人： Kamel Abouda ,  Laurent Guillot

发明人： Kamel Abouda ,  Laurent Guillot

IPC分类号： G06F1/04

CPC分类号： G01R29/0273 ,  G06F1/24

摘要： A clock circuit which may include a first clock input for receiving a first clock signal and a second clock input for receiving a second clock signal. A clock calibration unit is connected to the first clock input and the second clock input. The calibration unit may calibrate the second clock signal relative to the first clock signal. The clock calibration unit may have a calibration output for outputting a calibrated clock signal. The clock circuit may include a switch unit connected to the first clock input and the calibration output. The switch unit can select a selected clock signal selected from the first clock signal and the calibrated signal. The switch unit has a switch output for outputting the selected clock signal. A switch control unit is connected to the switch unit for controlling which signal is selected based on a selection criterion and a clock circuit output is connected to the switch unit for outputting the selected clock signal.

摘要翻译： 时钟电路，其可以包括用于接收第一时钟信号的第一时钟输入和用于接收第二时钟信号的第二时钟输入。 时钟校准单元连接到第一个时钟输入和第二个时钟输入。 校准单元可以相对于第一时钟信号校准第二时钟信号。 时钟校准单元可以具有用于输出校准时钟信号的校准输出。 时钟电路可以包括连接到第一时钟输入和校准输出的开关单元。 开关单元可以选择从第一时钟信号和校准信号中选择的所选择的时钟信号。 开关单元具有用于输出所选择的时钟信号的开关输出。 开关控制单元连接到开关单元，用于基于选择标准控制哪个信号被选择，并且时钟电路输出连接到开关单元以输出所选择的时钟信号。

公开(公告)号：US20100244902A1

公开(公告)日：2010-09-30

申请号：US12294799

申请日：2007-01-08

申请人： Kamel Abouda ,  Laurent Guillot

发明人： Kamel Abouda ,  Laurent Guillot

IPC分类号： G06F1/04

CPC分类号： G01R29/0273 ,  G06F1/24

摘要： A clock circuit which may include a first clock input for receiving a first clock signal and a second clock input for receiving a second clock signal. A clock calibration unit is connected to the first clock input and the second clock input. The calibration unit may calibrate the second clock signal relative to the first clock signal. The clock calibration unit may have a calibration output for outputting a calibrated clock signal. The clock circuit may include a switch unit connected to the first clock input and the calibration output. The switch unit can select a selected clock signal selected from the first clock signal and the calibrated signal. The switch unit has a switch output for outputting the selected clock signal. A switch control unit is connected to the switch unit for controlling which signal is selected based on a selection criterion and a clock circuit output is connected to the switch unit for outputting the selected clock signal.

摘要翻译： 时钟电路，其可以包括用于接收第一时钟信号的第一时钟输入和用于接收第二时钟信号的第二时钟输入。 时钟校准单元连接到第一个时钟输入和第二个时钟输入。 校准单元可以相对于第一时钟信号校准第二时钟信号。 时钟校准单元可以具有用于输出校准时钟信号的校准输出。 时钟电路可以包括连接到第一时钟输入和校准输出的开关单元。 开关单元可以选择从第一时钟信号和校准信号中选择的所选择的时钟信号。 开关单元具有用于输出所选择的时钟信号的开关输出。 开关控制单元连接到开关单元，用于基于选择标准控制哪个信号被选择，并且时钟电路输出连接到开关单元以输出所选择的时钟信号。