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公开(公告)号:US20160179545A1
公开(公告)日:2016-06-23
申请号:US14581268
申请日:2014-12-23
申请人: Kamil Garifullin , Stanislav Shwartsman , Lihu Rappoport , Zeev Sperber , Pavel I. Kryukov , Andrey Kluchnikov , Igor Yanover , George Leifman , Alex Gerber , Jared W. Stark
发明人: Kamil Garifullin , Stanislav Shwartsman , Lihu Rappoport , Zeev Sperber , Pavel I. Kryukov , Andrey Kluchnikov , Igor Yanover , George Leifman , Alex Gerber , Jared W. Stark
IPC分类号: G06F9/38
CPC分类号: G06F9/384 , G06F9/30043 , G06F9/30101 , G06F9/30116 , G06F9/3802 , G06F9/3824 , G06F9/3826 , G06F9/3836 , G06F9/3838 , G06F9/3891
摘要: A processor includes a core, a memory subsystem, a predictor module, and a memory rename module. The predictor module may include a first logic to identify a dependency between a store instruction and a load instruction, and a second logic to assign a memory renaming (MRN) register to the store instruction and the load instruction based on the identified dependency. Further, the memory rename module may include a third logic to copy, based on the assigned MRN register, information in a first logical register associated with the store instruction directly to a second logical register associated with the load instruction.
摘要翻译: 处理器包括核心,存储器子系统,预测器模块和存储器重命名模块。 预测器模块可以包括用于识别存储指令和加载指令之间的依赖性的第一逻辑,以及基于所识别的依赖关系将存储器重命名(MRN)寄存器分配给存储指令和加载指令的第二逻辑。 此外,存储器重命名模块可以包括第三逻辑,用于基于所分配的MRN寄存器将与存储指令相关联的第一逻辑寄存器中的信息直接复制到与加载指令相关联的第二逻辑寄存器。
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公开(公告)号:US09811340B2
公开(公告)日:2017-11-07
申请号:US13525825
申请日:2012-06-18
申请人: Nikolay Kosarev , Jayesh Iyer , Sergey Shishlov , Andrey Kluchnikov , Alexander Butuzov , Boris A. Babayan , Vladimir Penkovski , Sergey V. Bulenkov
发明人: Nikolay Kosarev , Jayesh Iyer , Sergey Shishlov , Andrey Kluchnikov , Alexander Butuzov , Boris A. Babayan , Vladimir Penkovski , Sergey V. Bulenkov
CPC分类号: G06F9/38 , G06F9/321 , G06F9/3834 , G06F9/3851 , G06F9/3855
摘要: A computer system, a processor in a computer and a computer-implemented method executable on a computer processor involve dividing a set of computer instructions arranged in a sequential program order into a plurality of instruction sequences. Instructions within each sequence are arranged according to the program order. An increment value is assigned to a preceding instruction in each sequence. The increment value is equal to a difference between a program order value of a subsequent instruction in the sequence and a program order value of the preceding instruction. The processor calculates the program order value of each subsequent instruction based on the program order value and the increment value of a corresponding preceding instruction in the same sequence.
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