公开(公告)号：US09811340B2

公开(公告)日：2017-11-07

申请号：US13525825

申请日：2012-06-18

申请人： Nikolay Kosarev ,  Jayesh Iyer ,  Sergey Shishlov ,  Andrey Kluchnikov ,  Alexander Butuzov ,  Boris A. Babayan ,  Vladimir Penkovski ,  Sergey V. Bulenkov

发明人： Nikolay Kosarev ,  Jayesh Iyer ,  Sergey Shishlov ,  Andrey Kluchnikov ,  Alexander Butuzov ,  Boris A. Babayan ,  Vladimir Penkovski ,  Sergey V. Bulenkov

IPC分类号： G06F9/38 ,  G06F9/32

CPC分类号： G06F9/38 ,  G06F9/321 ,  G06F9/3834 ,  G06F9/3851 ,  G06F9/3855

摘要： A computer system, a processor in a computer and a computer-implemented method executable on a computer processor involve dividing a set of computer instructions arranged in a sequential program order into a plurality of instruction sequences. Instructions within each sequence are arranged according to the program order. An increment value is assigned to a preceding instruction in each sequence. The increment value is equal to a difference between a program order value of a subsequent instruction in the sequence and a program order value of the preceding instruction. The processor calculates the program order value of each subsequent instruction based on the program order value and the increment value of a corresponding preceding instruction in the same sequence.

公开(公告)号：US20130339679A1

公开(公告)日：2013-12-19

申请号：US13524240

申请日：2012-06-15

申请人： Jayesh IYER ,  Nikolay Kosarev ,  Sergey Shishlov ,  Alexey Sivtsov ,  Alexander Butuzov ,  Boris A. Babayan ,  Vladimir Penkovski

发明人： Jayesh IYER ,  Nikolay Kosarev ,  Sergey Shishlov ,  Alexey Sivtsov ,  Alexander Butuzov ,  Boris A. Babayan ,  Vladimir Penkovski

IPC分类号： G06F9/30

CPC分类号： G06F9/30032 ,  G06F9/3814 ,  G06F9/3836 ,  G06F9/3838 ,  G06F9/3851 ,  G06F9/3857

摘要： A computer system, a computer processor and a method executable on a computer processor involve placing each sequence of a plurality of sequences of computer instructions being scheduled for execution in the processor into a separate queue. The head instruction from each queue is stored into a first storage unit prior to determining whether the head instruction is ready for scheduling. For each instruction in the first storage unit that is determined to be ready, the instruction is moved from the first storage unit to a second storage unit. During a first processor cycle, each instruction in the first storage unit that is determined to be not ready is retained in the first storage unit, and the determining of whether the instruction is ready is repeated during the next processor cycle. Scheduling logic performs scheduling of instructions contained in the second storage unit.

摘要翻译： 计算机系统，计算机处理器和可在计算机处理器上执行的方法包括将计划执行的计算机指令的多个序列的每个序列放置在处理器中以进入单独的队列。 在确定头部指令是否准备好进行调度之前，来自每个队列的头部指令被存储到第一存储单元中。 对于确定准备好的第一存储单元中的每个指令，指令从第一存储单元移动到第二存储单元。 在第一处理器周期期间，确定未准备好的第一存储单元中的每个指令被保留在第一存储单元中，并且在下一处理器周期期间重复确定指令是否就绪。 调度逻辑执行包含在第二存储单元中的指令的调度。

公开(公告)号：US09645819B2

公开(公告)日：2017-05-09

申请号：US13524240

申请日：2012-06-15

申请人： Jayesh Iyer ,  Nikolay Kosarev ,  Sergey Shishlov ,  Alexey Sivtsov ,  Alexander Butuzov ,  Boris A. Babayan ,  Vladimir Penkovski

发明人： Jayesh Iyer ,  Nikolay Kosarev ,  Sergey Shishlov ,  Alexey Sivtsov ,  Alexander Butuzov ,  Boris A. Babayan ,  Vladimir Penkovski

IPC分类号： G06F9/38 ,  G06F9/30

CPC分类号： G06F9/30032 ,  G06F9/3814 ,  G06F9/3836 ,  G06F9/3838 ,  G06F9/3851 ,  G06F9/3857

摘要： A computer system, a computer processor and a method executable on a computer processor involve placing each sequence of a plurality of sequences of computer instructions being scheduled for execution in the processor into a separate queue. The head instruction from each queue is stored into a first storage unit prior to determining whether the head instruction is ready for scheduling. For each instruction in the first storage unit that is determined to be ready, the instruction is moved from the first storage unit to a second storage unit. During a first processor cycle, each instruction in the first storage unit that is determined to be not ready is retained in the first storage unit, and the determining of whether the instruction is ready is repeated during the next processor cycle. Scheduling logic performs scheduling of instructions contained in the second storage unit.

公开(公告)号：US20140208074A1

公开(公告)日：2014-07-24

申请号：US13993552

申请日：2012-03-30

申请人： Boris A. Babayan ,  Vladimir Pentkovski ,  Jayesh Iyer ,  Nikolay Kosarev ,  Sergey Y. Shishlov ,  Alexander V. Butuzov ,  Alexey Y. Sivtsov

发明人： Boris A. Babayan ,  Vladimir Pentkovski ,  Jayesh Iyer ,  Nikolay Kosarev ,  Sergey Y. Shishlov ,  Alexander V. Butuzov ,  Alexey Y. Sivtsov

IPC分类号： G06F9/30

CPC分类号： G06F9/30145 ,  G06F9/3838 ,  G06F9/3851 ,  G06F9/3857

摘要： In one embodiment, a multi-strand system with a pipeline includes a front-end unit, an instruction scheduling unit (ISU), and a back-end unit. The front-end unit performs an out-of-order fetch of interdependent instructions queued using a front-end buffer. The ISU dedicates two hardware entries per strand for checking operand-readiness of an instruction and for determining an execution port to which the instruction is dispatched. The back-end unit receives instructions dispatched from the hardware device and stores the instructions until they are executed. Other embodiments are described and claimed.

摘要翻译： 在一个实施例中，具有流水线的多股系统包括前端单元，指令调度单元（ISU）和后端单元。 前端单元执行使用前端缓冲区排队的相互依赖的指令的无序读取。 ISU专用于每条链路的两个硬件条目，用于检查指令的操作数准备状态以及确定指令发送到的执行端口。 后端单元接收从硬件设备发出的指令，并存储指令直到执行。 描述和要求保护其他实施例。

公开(公告)号：US20130007415A1

公开(公告)日：2013-01-03

申请号：US13175619

申请日：2011-07-01

申请人： Boris A. Babayan ,  Vladimir M. Pentkovski ,  Alexander V. Butuzov ,  Sergey Y. Shishlov ,  Alexey Y. Sivtsov ,  Nikolay E. Kosarev

发明人： Boris A. Babayan ,  Vladimir M. Pentkovski ,  Alexander V. Butuzov ,  Sergey Y. Shishlov ,  Alexey Y. Sivtsov ,  Nikolay E. Kosarev

IPC分类号： G06F9/30

CPC分类号： G06F9/3855 ,  G06F9/30087 ,  G06F9/3016 ,  G06F9/3017 ,  G06F9/34 ,  G06F9/3802 ,  G06F9/3824 ,  G06F9/3838 ,  G06F9/3851 ,  G06F9/3891

摘要： In accordance with embodiments disclosed herein, there are provided methods, systems, and apparatuses for scheduling instructions in a multi-strand out-of-order processor. For example, an apparatus for scheduling instructions in a multi-strand out-of-order processor includes an out-of-order instruction fetch unit to retrieve a plurality of interdependent instructions for execution from a multi-strand representation of a sequential program listing; an instruction scheduling unit to schedule the execution of the plurality of interdependent instructions based at least in part on operand synchronization bits encoded within each of the plurality of interdependent instructions; and a plurality of execution units to execute at least a subset of the plurality of interdependent instructions in parallel.

摘要翻译： 根据本文公开的实施例，提供了用于在多股无序处理器中调度指令的方法，系统和装置。 例如，用于在多股无序处理器中调度指令的装置包括：无序指令获取单元，用于从顺序程序列表的多链表示中检索用于执行的多个相互依赖的指令; 指令调度单元，至少部分地基于在所述多个相互依赖的指令中的每一个内编码的操作数同步位来调度所述多个相互依赖指令的执行; 以及并行执行多个相互依赖指令的至少一个子集的多个执行单元。

公开(公告)号：US09529596B2

公开(公告)日：2016-12-27

申请号：US13175619

申请日：2011-07-01

申请人： Boris A. Babayan ,  Vladimir M. Pentkovski ,  Alexander V. Butuzov ,  Sergey Y. Shishlov ,  Alexey Y. Sivtsov ,  Nikolay E. Kosarev

发明人： Boris A. Babayan ,  Vladimir M. Pentkovski ,  Alexander V. Butuzov ,  Sergey Y. Shishlov ,  Alexey Y. Sivtsov ,  Nikolay E. Kosarev

IPC分类号： G06F9/38 ,  G06F9/30

CPC分类号： G06F9/3855 ,  G06F9/30087 ,  G06F9/3016 ,  G06F9/3017 ,  G06F9/34 ,  G06F9/3802 ,  G06F9/3824 ,  G06F9/3838 ,  G06F9/3851 ,  G06F9/3891

摘要： In accordance with embodiments disclosed herein, there are provided methods, systems, and apparatuses for scheduling instructions in a multi-strand out-of-order processor. For example, an apparatus for scheduling instructions in a multi-strand out-of-order processor includes an out-of-order instruction fetch unit to retrieve a plurality of interdependent instructions for execution from a multi-strand representation of a sequential program listing; an instruction scheduling unit to schedule the execution of the plurality of interdependent instructions based at least in part on operand synchronization bits encoded within each of the plurality of interdependent instructions; and a plurality of execution units to execute at least a subset of the plurality of interdependent instructions in parallel.

摘要翻译： 根据本文公开的实施例，提供了用于在多股无序处理器中调度指令的方法，系统和装置。 例如，用于在多股无序处理器中调度指令的装置包括：无序指令获取单元，用于从顺序程序列表的多链表示中检索用于执行的多个相互依赖的指令; 指令调度单元，至少部分地基于在所述多个相互依赖的指令中的每一个内编码的操作数同步位来调度所述多个相互依赖指令的执行; 以及并行执行多个相互依赖指令的至少一个子集的多个执行单元。