公开(公告)号：US20130178022A1

公开(公告)日：2013-07-11

申请号：US13618186

申请日：2012-09-14

申请人： Kangguo CHENG ,  Ali KHAKIFIROOZ ,  Sivananda KANAKASABAPATHY ,  Pranita KULKARNI ,  Balasubramanian S. HARAN

发明人： Kangguo CHENG ,  Ali KHAKIFIROOZ ,  Sivananda KANAKASABAPATHY ,  Pranita KULKARNI ,  Balasubramanian S. HARAN

IPC分类号： H01L21/336

CPC分类号： H01L29/66795 ,  H01L29/66545 ,  H01L29/7848 ,  H01L29/785

摘要： A method is provided for fabricating a transistor. According to the method, a second semiconductor layer is formed on a first semiconductor layer, and a dummy gate structure is formed on the second semiconductor layer. A gate spacer is formed on sidewalls of the dummy gate structure, and the dummy gate structure is removed to form a cavity. The second semiconductor layer beneath the cavity is removed. A gate dielectric is formed on the first portion of the first semiconductor layer and adjacent to the sidewalls of the second semiconductor layer and sidewalls of the gate spacer. A gate conductor is formed on the first portion of the gate dielectric and abutting the second portion of the gate dielectric. Raised source/drain regions are formed in the second semiconductor layer, with at least part of the raised source/drain regions being below the gate spacer.

摘要翻译： 提供了一种用于制造晶体管的方法。 根据该方法，在第一半导体层上形成第二半导体层，在第二半导体层上形成虚拟栅极结构。 栅极间隔件形成在虚拟栅极结构的侧壁上，并且去除虚拟栅极结构以形成空腔。 除去腔下方的第二半导体层。 栅电介质形成在第一半导体层的第一部分上并且邻近第二半导体层的侧壁和栅极间隔物的侧壁。 栅极导体形成在栅极电介质的第一部分上并邻接栅极电介质的第二部分。 凸起的源/漏区形成在第二半导体层中，其中至少部分凸起的源极/漏极区在栅极间隔物之下。

公开(公告)号：US20130005129A1

公开(公告)日：2013-01-03

申请号：US13612069

申请日：2012-09-12

申请人： Sivananda KANAKASABAPATHY ,  Hemanth JAGANNATHAN ,  Geng WANG

发明人： Sivananda KANAKASABAPATHY ,  Hemanth JAGANNATHAN ,  Geng WANG

IPC分类号： H01L21/283

CPC分类号： H01L27/10826 ,  H01L21/26586 ,  H01L21/845 ,  H01L27/10879 ,  H01L27/10891 ,  H01L27/1211

摘要： Various embodiment integrate embedded dynamic random access memory with fin field effect transistors. In one embodiment, a first fin structure and at least a second fin structure are formed on a substrate. A deep trench area is formed between the first and second fin structures. A high-k metal gate is formed within the deep trench area. The high-k metal gate includes a high-k dielectric layer and a metal layer. A polysilicon material is deposited within the deep trench area adjacent to the metal layer. The high-k metal gate and the polysilicon material are recessed and etched to an area below a top surface of a substrate insulator layer. A poly strap is formed in the deep trench area. The poly strap is dimensioned to be below a top surface of the first and second fin structures. The first and second fin structures are electrically coupled to the poly strap.

摘要翻译： 各种实施例将嵌入式动态随机存取存储器与鳍式场效应晶体管集成。 在一个实施例中，在衬底上形成第一鳍结构和至少第二鳍结构。 在第一和第二翅片结构之间形成深沟槽区域。 在深沟槽区域内形成高k金属栅极。 高k金属栅极包括高k电介质层和金属层。 多晶硅材料沉积在与金属层相邻的深沟槽区域内。 高k金属栅极和多晶硅材料被凹入并蚀刻到衬底绝缘体层的顶表面下方的区域。 在深沟槽区域中形成多晶带。 该多晶带的尺寸设计成在第一和第二鳍结构的顶表面下方。 第一和第二翅片结构电耦合到多晶带。

公开(公告)号：US20140030864A1

公开(公告)日：2014-01-30

申请号：US13556437

申请日：2012-07-24

申请人： Veeraraghavan S. BASKER ,  Sivananda KANAKASABAPATHY ,  Tenko YAMASHITA ,  Chun-Chen YEH

发明人： Veeraraghavan S. BASKER ,  Sivananda KANAKASABAPATHY ,  Tenko YAMASHITA ,  Chun-Chen YEH

IPC分类号： H01L21/02

CPC分类号： H01L27/10867 ,  H01L21/845 ,  H01L27/10826 ,  H01L27/1087 ,  H01L27/10879 ,  H01L27/1211

摘要： The specification and drawings present a new method, device and computer/software related product (e.g., a computer readable memory) are presented for realizing eDRAM strap formation in Fin FET device structures. Semiconductor on insulator (SOI) substrate comprising at least an insulator layer between a first semiconductor layer and a second semiconductor layer is provided. The (metal) strap formation is accomplished by depositing conductive layer on fins portion of the second semiconductor layer (Si) and a semiconductor material (polysilicon) in each DT capacitor extending to the second semiconductor layer. The metal strap is sealed by a nitride spacer to prevent the shorts between PWL and DT capacitors.

摘要翻译： 说明书和附图提出了一种新的方法，设备和计算机/软件相关产品（例如，计算机可读存储器），用于实现Fin FET器件结构中的eDRAM带形成。 提供了在第一半导体层和第二半导体层之间至少包括绝缘体层的半导体绝缘体（SOI）衬底。 （金属）带形成是通过在第二半导体层（Si）的鳍部分上沉积导电层和延伸到第二半导体层的每个DT电容器中的半导体材料（多晶硅）来实现的。 金属带由氮化物间隔物密封，以防止PWL和DT电容器之间的短路。

公开(公告)号：US20120329268A1

公开(公告)日：2012-12-27

申请号：US13424932

申请日：2012-03-20

申请人： Eiichi SODA ,  Yunpeng YIN ,  Sivananda KANAKASABAPATHY

发明人： Eiichi SODA ,  Yunpeng YIN ,  Sivananda KANAKASABAPATHY

IPC分类号： H01L21/768

CPC分类号： H01L21/31144 ,  H01L21/0337 ,  H01L21/76811 ,  H01L21/76816 ,  H01L21/76897

摘要： An improved method of making interconnect structures with self-aligned vias in semiconductor devices utilizes sidewall image transfer to define the trench pattern. The sidewall height acts as a sacrificial mask during etching of the via and subsequent etching of the trench, so that the underlying metal hard mask is protected. Thinner hard masks and/or a wider range of etch chemistries may thereby be utilized.

摘要翻译： 在半导体器件中制造具有自对准通孔的互连结构的改进方法利用侧壁图像转移来限定沟槽图案。 在蚀刻通孔和​​随后蚀刻沟槽期间，侧壁高度用作牺牲掩模，使得下面的金属硬掩模被保护。 因此可以利用更薄的硬掩模和/或更广泛的蚀刻化学物质。