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    Design Structures Incorporating Semiconductor Device Structures with Reduced Junction Capacitance and Drain Induced Barrier Lowering
    2.
    发明申请
    Design Structures Incorporating Semiconductor Device Structures with Reduced Junction Capacitance and Drain Induced Barrier Lowering 有权
    结合具有减少的结电容和漏极诱导的阻挡层的半导体器件结构的设计结构

    公开(公告)号：US20080034335A1

    公开(公告)日：2008-02-07

    申请号：US11875013

    申请日：2007-10-19

    申请人： Kangguo Cheng ,  Louis Hsu ,  Jack Mandelman ,  Haining Yang

    发明人： Kangguo Cheng ,  Louis Hsu ,  Jack Mandelman ,  Haining Yang

    IPC分类号： G11C29/54

    CPC分类号： H01L29/78603 ,  G11C29/54 ,  H01L29/51 ,  H01L29/513 ,  H01L29/66545 ,  H01L29/66636 ,  H01L29/66772

    摘要： Design structure embodied in a machine readable medium for designing, manufacturing, or testing a design. The design structure includes semiconductor device structures characterized by reduced junction capacitance and drain induced barrier lowering. The semiconductor device structure of the design structure includes a semiconductor layer and a dielectric layer disposed between the semiconductor layer and the substrate. The dielectric layer includes a first dielectric region with a first dielectric constant and a second dielectric region with a second dielectric constant that is greater than the first dielectric constant.

    摘要翻译： 用于设计，制造或测试设计的机器可读介质中体现的设计结构。 该设计结构包括半导体器件结构，其特征在于结电容减小和漏极引起的栅极降低。 设计结构的半导体器件结构包括设置在半导体层和衬底之间的半导体层和介电层。 电介质层包括具有第一介电常数的第一电介质区域和具有大于第一介电常数的第二介电常数的第二电介质区域。

    SEMICONDUCTOR DEVICE STRUCTURES WITH REDUCED JUNCTION CAPACITANCE AND DRAIN INDUCED BARRIER LOWERING AND METHODS FOR FABRICATING SUCH DEVICE STRUCTURES AND FOR FABRICATING A SEMICONDUCTOR-ON-INSULATOR SUBSTRATE
    3.
    发明申请
    SEMICONDUCTOR DEVICE STRUCTURES WITH REDUCED JUNCTION CAPACITANCE AND DRAIN INDUCED BARRIER LOWERING AND METHODS FOR FABRICATING SUCH DEVICE STRUCTURES AND FOR FABRICATING A SEMICONDUCTOR-ON-INSULATOR SUBSTRATE 失效
    具有降低的接合电容和漏极诱发障碍物下降的半导体器件结构以及用于制造这种器件结构和用于制造半导体绝缘体衬底的方法

    公开(公告)号：US20070246752A1

    公开(公告)日：2007-10-25

    申请号：US11379655

    申请日：2006-04-21

    申请人： Kangguo Cheng ,  Louis Hsu ,  Jack Mandelman ,  Haining Yang

    发明人： Kangguo Cheng ,  Louis Hsu ,  Jack Mandelman ,  Haining Yang

    IPC分类号： H01L29/76

    CPC分类号： H01L29/66545 ,  H01L29/51 ,  H01L29/513 ,  H01L29/66636 ,  H01L29/66772 ,  H01L29/78603 ,  Y10S438/96

    摘要： Semiconductor device structures with reduced junction capacitance and drain induced barrier lowering, methods for fabricating such device structures, and methods for forming a semiconductor-on-insulator substrate. The semiconductor structure comprises a semiconductor layer and a dielectric layer disposed between the semiconductor layer and the substrate. The dielectric layer includes a first dielectric region with a first dielectric constant and a second dielectric region with a second dielectric constant that is greater than the first dielectric constant. In one embodiment, the dielectric constant of the first dielectric region may be less than about 3.9 and the dielectric constant of the second dielectric region may be greater than about ten (10). The semiconductor-on-insulator substrate comprises a semiconductor layer separated from a bulk layer by an insulator layer of a high-dielectric constant material. The fabrication methods comprise modifying a region of the dielectric layer to have a lower dielectric constant.

    摘要翻译： 具有减小的结电容和漏极引起的屏障降低的半导体器件结构，用于制造这种器件结构的方法以及用于形成绝缘体上半导体衬底的方法。 半导体结构包括半导体层和设置在半导体层和衬底之间的电介质层。 电介质层包括具有第一介电常数的第一电介质区域和具有大于第一介电常数的第二介电常数的第二电介质区域。 在一个实施例中，第一电介质区域的介电常数可以小于约3.9，并且第二电介质区域的介电常数可以大于约十（10）。 绝缘体上半导体衬底包括通过高介电常数材料的绝缘体层与本体层分离的半导体层。 制造方法包括修改介电层的区域以具有较低的介电常数。

    PFETS and methods of manufacturing the same
    4.
    发明申请
    PFETS and methods of manufacturing the same 失效
    PFETS及其制造方法

    公开(公告)号：US20070166890A1

    公开(公告)日：2007-07-19

    申请号：US11335763

    申请日：2006-01-19

    申请人： Kangguo Cheng ,  Louis Hsu ,  Jack Mandelman ,  Haining Yang

    发明人： Kangguo Cheng ,  Louis Hsu ,  Jack Mandelman ,  Haining Yang

    IPC分类号： H01L21/84

    CPC分类号： H01L29/66742 ,  H01L29/165 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66636 ,  H01L29/7848 ,  H01L29/78687

    摘要： In a first aspect, a first method of manufacturing a PFET on a substrate is provided. The first method includes the steps of (1) forming a gate channel region of the PFET having a first thickness on the substrate; and (2) forming at least one composite source/drain diffusion region of the PFET having a second thickness greater than the first thickness on the substrate. The at least one composite source/drain diffusion region is adapted to cause a strain in the gate channel region. Further, significantly all of the at least one composite source/drain diffusion region is below a bottom surface of a gate of the PFET. Numerous other aspects are provided.

    摘要翻译： 在第一方面中，提供了在衬底上制造PFET的第一种方法。 第一种方法包括以下步骤：（1）在衬底上形成具有第一厚度的PFET的栅极沟道区; 和（2）在衬底上形成具有大于第一厚度的第二厚度的PFET的至少一个复合源极/漏极扩散区域。 至少一个复合源极/漏极扩散区域适于在栅极沟道区域引起应变。 此外，显着地所有的至少一个复合源极/漏极扩散区域在PFET的栅极的底表面之下。 提供了许多其他方面。

    Semiconductor device structures with self-aligned doped regions and methods for forming such semiconductor device structures
    6.
    发明申请
    Semiconductor device structures with self-aligned doped regions and methods for forming such semiconductor device structures 失效
    具有自对准掺杂区域的半导体器件结构和用于形成这种半导体器件结构的方法

    公开(公告)号：US20070235833A1

    公开(公告)日：2007-10-11

    申请号：US11393142

    申请日：2006-03-30

    申请人： Kangguo Cheng ,  Louis Hsu ,  Jack Mandelman

    发明人： Kangguo Cheng ,  Louis Hsu ,  Jack Mandelman

    IPC分类号： H01L29/00

    CPC分类号： H01L27/10841 ,  H01L27/10864

    摘要： Semiconductor device structures with self-aligned doped regions and methods for forming such semiconductor device structures. The semiconductor structure comprises first and second doped regions of a first conductivity type defined in the semiconductor material of a substrate bordering a sidewall of a trench. An intervening region of the semiconductor material separates the first and second doped regions. A third doped region is defined in the semiconductor material bordering the sidewall of the trench and disposed between the first and second doped regions. The third doped region is doped to have a second conductivity type opposite to the first conductivity type. Methods for forming the doped regions involve depositing either a layer of a material doped with both dopants or different layers each doped with one of the dopants in the trench and, then, diffusing the dopants from the layer or layers into the semiconductor material bordering the trench sidewall.

    摘要翻译： 具有自对准掺杂区域的半导体器件结构和用于形成这种半导体器件结构的方法。 半导体结构包括限定在与沟槽的侧壁相邻的衬底的半导体材料中的第一导电类型的第一和第二掺杂区域。 半导体材料的中间区域分离第一和第二掺杂区域。 第三掺杂区域限定在与沟槽的侧壁接壤并且设置在第一和第二掺杂区域之间的半导体材料中。 第三掺杂区被掺杂以具有与第一导电类型相反的第二导电类型。 用于形成掺杂区域的方法包括沉积掺杂有掺杂剂或不同层的材料的层，每个掺杂剂或不同的层在沟槽中掺杂有一种掺杂剂，然后将掺杂剂从层或层扩散到与沟槽接壤的半导体材料 侧壁。

    Design Structures Incorporating Semiconductor Device Structures with Self-Aligned Doped Regions
    7.
    发明申请
    Design Structures Incorporating Semiconductor Device Structures with Self-Aligned Doped Regions 审中-公开
    将半导体器件结构与自对准掺杂区域结合的设计结构

    公开(公告)号：US20080048186A1

    公开(公告)日：2008-02-28

    申请号：US11876116

    申请日：2007-10-22

    申请人： Kangguo Cheng ,  Louis Hsu ,  Jack Mandelman

    发明人： Kangguo Cheng ,  Louis Hsu ,  Jack Mandelman

    IPC分类号： H01L23/58

    CPC分类号： H01L27/10841 ,  H01L27/10864 ,  H01L2924/0002 ,  H01L2924/00

    摘要： Design structure embodied in a machine readable medium for designing, manufacturing, or testing a design in which the design structure includes semiconductor device structures with self-aligned doped regions. The semiconductor structure may include first and second doped regions of a first conductivity type defined in the semiconductor material of a substrate bordering a sidewall of a trench. An intervening region of the semiconductor material separates the first and second doped regions. A third doped region is defined in the semiconductor material bordering the sidewall of the trench and disposed between the first and second doped regions. The third doped region is doped to have a second conductivity type opposite to the first conductivity type.

    摘要翻译： 设计结构体现在用于设计，制造或测试其中设计结构包括具有自对准掺杂区域的半导体器件结构的设计的机器可读介质中。 半导体结构可以包括限定在与沟槽的侧壁接合的衬底的半导体材料中的第一导电类型的第一和第二掺杂区域。 半导体材料的中间区域分离第一和第二掺杂区域。 第三掺杂区域限定在与沟槽的侧壁接壤并且设置在第一和第二掺杂区域之间的半导体材料中。 第三掺杂区被掺杂以具有与第一导电类型相反的第二导电类型。

    BODY-CONTACTED SEMICONDUCTOR STRUCTURES AND METHODS OF FABRICATING SUCH BODY-CONTACTED SEMICONDUCTOR STRUCTURES
    8.
    发明申请
    BODY-CONTACTED SEMICONDUCTOR STRUCTURES AND METHODS OF FABRICATING SUCH BODY-CONTACTED SEMICONDUCTOR STRUCTURES 失效
    人体接触半导体结构和制造这种接触式半导体结构的方法

    公开(公告)号：US20080044959A1

    公开(公告)日：2008-02-21

    申请号：US11925352

    申请日：2007-10-26

    申请人： Kangguo Cheng ,  Louis Hsu ,  Jack Mandelman

    发明人： Kangguo Cheng ,  Louis Hsu ,  Jack Mandelman

    IPC分类号： H01L21/86

    CPC分类号： H01L21/84 ,  H01L27/0218 ,  H01L27/10841 ,  H01L27/1203 ,  H01L29/66545

    摘要： A semiconductor structure for a dynamic random access memory (DRAM) cell array that includes a plurality of vertical memory cells built on a semiconductor-on-insulator (SOI) wafer and a body contact in the buried dielectric layer of the SOI wafer. The body contact electrically couples a semiconductor body with a channel region of the access device of one vertical memory cell and a semiconductor substrate of the SOI wafer. The body contact provides a current leakage path that reduces the impact of floating body effects upon the vertical memory cell. The body contact may be formed by an ion implantation process that modifies the stoichiometry of a region of the buried dielectric layer so that the modified region becomes electrically conductive with a relatively high resistance.

    摘要翻译： 一种用于动态随机存取存储器（DRAM）单元阵列的半导体结构，其包括建立在绝缘体上半导体（SOI）晶片上的多个垂直存储单元和SOI晶片的埋入介质层中的体接触。 体接触将半导体本体与一个垂直存储单元的存取器件的沟道区和SOI晶片的半导体衬底电耦合。 身体接触提供了一种电流泄漏路径，可减少浮体对垂直记忆体的影响。 体接触可以通过离子注入工艺形成，该方法改变掩埋介电层的区域的化学计量，使得改性区域以相对较高的电阻变为导电性。

    Ferromagnetic memory cell and methods of making and using the same
    9.
    发明申请
    Ferromagnetic memory cell and methods of making and using the same 有权
    铁磁记忆单元及其制造和使用方法

    公开(公告)号：US20070045686A1

    公开(公告)日：2007-03-01

    申请号：US11216387

    申请日：2005-08-31

    申请人： Kangguo Cheng ,  Herbert Ho ,  Louis Hsu ,  Jack Mandelman

    发明人： Kangguo Cheng ,  Herbert Ho ,  Louis Hsu ,  Jack Mandelman

    IPC分类号： H01L29/94

    CPC分类号： G11C11/15 ,  H01L27/1203 ,  H01L43/065

    摘要： In a first aspect, a first apparatus is provided. The first apparatus is a memory cell that includes (1) a semiconductor fin enclosure formed on an insulating layer of a substrate; and (2) a ferromagnetic material within the semiconductor fin enclosure. A top surface of the ferromagnetic material is below a top surface of the semiconductor fin enclosure. Numerous other aspects are provided.

    摘要翻译： 在第一方面中，提供了一种第一装置。 第一装置是存储单元，其包括：（1）形成在基板的绝缘层上的半导体翅片外壳; 和（2）半导体翅片外壳内的铁磁材料。 铁磁材料的顶表面位于半导体翅片外壳的顶表面之下。 提供了许多其他方面。

    Body-contacted semiconductor structures and methods of fabricating such body-contacted semiconductor structures
    10.
    发明申请
    Body-contacted semiconductor structures and methods of fabricating such body-contacted semiconductor structures 审中-公开
    体接触半导体结构和制造这种体接触半导体结构的方法

    公开(公告)号：US20070045697A1

    公开(公告)日：2007-03-01

    申请号：US11216386

    申请日：2005-08-31

    申请人： Kangguo Cheng ,  Louis Hsu ,  Jack Mandelman

    发明人： Kangguo Cheng ,  Louis Hsu ,  Jack Mandelman

    IPC分类号： H01L27/108

    CPC分类号： H01L21/84 ,  H01L27/0218 ,  H01L27/10841 ,  H01L27/1203 ,  H01L29/66545

    摘要： A semiconductor structure for a dynamic random access memory (DRAM) cell array that includes a plurality of vertical memory cells built on a semiconductor-on-insulator (SOI) wafer and a body contact in the buried dielectric layer of the SOI wafer. The body contact electrically couples a semiconductor body with a channel region of the access device of one vertical memory cell and a semiconductor substrate of the SOI wafer. The body contact provides a current leakage path that reduces the impact of floating body effects upon the vertical memory cell. The body contact may be formed by an ion implantation process that modifies the stoichiometry of a region of the buried dielectric layer so that the modified region becomes electrically conductive with a relatively high resistance.

    摘要翻译： 一种用于动态随机存取存储器（DRAM）单元阵列的半导体结构，其包括建立在绝缘体上半导体（SOI）晶片上的多个垂直存储单元和SOI晶片的埋入介质层中的体接触。 体接触将半导体本体与一个垂直存储单元的存取器件的沟道区和SOI晶片的半导体衬底电耦合。 身体接触提供了一种电流泄漏路径，可减少浮体对垂直记忆体的影响。 体接触可以通过离子注入工艺形成，该方法改变掩埋介电层的区域的化学计量，使得改性区域以相对较高的电阻变为导电性。