公开(公告)号：US20100325368A1

公开(公告)日：2010-12-23

申请号：US12486308

申请日：2009-06-17

申请人： Kari Ann O'Brien ,  George Lattimore ,  Joern Soerensen ,  Mathew B. Rutledge ,  Paul William Hollis

发明人： Kari Ann O'Brien ,  George Lattimore ,  Joern Soerensen ,  Mathew B. Rutledge ,  Paul William Hollis

IPC分类号： G06F12/00 ,  G06F12/02

CPC分类号： G06F13/1652

摘要： An apparatus includes a first processor that accesses memory according to a first clock frequency, a second processor that accesses memory according to a second clock frequency, and a memory device is configurable to selectively operate according to the first clock frequency or the second clock frequency. A memory controller enables dynamic configuration of organization of the memory device to allow a first portion of the memory device to be accessed by the first processor according to the first clock frequency and a second portion of the memory device to be accessed by the second processor according to the second clock frequency.

摘要翻译： 一种装置包括根据第一时钟频率访问存储器的第一处理器，根据第二时钟频率访问存储器的第二处理器，以及存储器件可配置为根据第一时钟频率或第二时钟频率选择性地操作。 存储器控制器实现对存储器设备的组织的动态配置，以允许第一处理器根据第一时钟频率访问存储器件的第一部分，并且由第二处理器访问存储器件的第二部分， 到第二个时钟频率。

公开(公告)号：US08296526B2

公开(公告)日：2012-10-23

申请号：US12486308

申请日：2009-06-17

申请人： Kari Ann O'Brien ,  George Lattimore ,  Joern Soersensen ,  Matthew B Rutledge ,  Paul William Hollis

发明人： Kari Ann O'Brien ,  George Lattimore ,  Joern Soersensen ,  Matthew B Rutledge ,  Paul William Hollis

IPC分类号： G06F12/00 ,  G06F13/00 ,  G06F13/28

CPC分类号： G06F13/1652

摘要： An apparatus includes a first processor that accesses memory according to a first clock frequency, a second processor that accesses memory according to a second clock frequency, and a memory device is configurable to selectively operate according to the first clock frequency or the second clock frequency. A memory controller enables dynamic configuration of organization of the memory device to allow a first portion of the memory device to be accessed by the first processor according to the first clock frequency and a second portion of the memory device to be accessed by the second processor according to the second clock frequency.

摘要翻译： 一种装置包括根据第一时钟频率访问存储器的第一处理器，根据第二时钟频率访问存储器的第二处理器，以及存储器件可配置为根据第一时钟频率或第二时钟频率选择性地操作。 存储器控制器实现对存储器设备的组织的动态配置，以允许第一处理器根据第一时钟频率访问存储器件的第一部分，并且由第二处理器访问存储器件的第二部分， 到第二个时钟频率。

公开(公告)号：US20060069894A1

公开(公告)日：2006-03-30

申请号：US10955609

申请日：2004-09-30

申请人： Paul Hollis ,  George Lattimore ,  Matthew Rutledge

发明人： Paul Hollis ,  George Lattimore ,  Matthew Rutledge

IPC分类号： G06F13/00

CPC分类号： G11C7/22 ,  G06F13/1689 ,  G11C7/1072 ,  G11C7/222 ,  G11C2207/2272 ,  G11C2207/2281 ,  G11C2207/229

摘要： A de-coupled memory access system including a memory access control circuit configured to generate first and second independent, de-coupled time references. The memory access control circuit includes a read initiate circuit responsive to the first time reference and a read signal for generating a read enable signal, and a write initiate circuit responsive to the second time reference and a write signal for generating a write enable signal independent of the read enable signal for providing independent, de-coupled write access to a memory array.

摘要翻译： 一种解耦耦合存储器存取系统，包括存储器访问控制电路，该存储器访问控制电路经配置以产​​生第一和第二独立的去耦合时间基准。 存储器访问控制电路包括响应于第一时间基准的读取启动电路和用于产生读取使能信号的读取信号，以及响应于第二时间基准的写入启动电路和用于产生独立于第 读使能信号，用于提供对存储器阵列的独立的去耦合的写访问。