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    Decoupled Shading Pipeline
    3.
    发明申请
    Decoupled Shading Pipeline 有权
    去耦阴影管道

    公开(公告)号：US20150170345A1

    公开(公告)日：2015-06-18

    申请号：US14103951

    申请日：2013-12-12

    申请人： Karthik Vaidyanathan ,  Marco Salvi ,  Robert M. Toth

    发明人： Karthik Vaidyanathan ,  Marco Salvi ,  Robert M. Toth

    IPC分类号： G06T5/00

    CPC分类号： G06T15/503 ,  G06T1/20 ,  G06T2200/12

    摘要： In some embodiments, a given frame or picture may have different shading rates. In one embodiment in some areas of the frame or picture the shading rate may be less than once per pixel and in other places it may be once per pixel. Examples where the shading rate may be reduced include areas where there is motion and camera defocus, areas of peripheral blur, and in general, any case where the visibility is reduced anyway. The shading rate may be changed in a region, such as a shading quad, by changing the size of the region.

    摘要翻译： 在一些实施例中，给定的帧或图片可以具有不同的着色速率。 在一个实施例中，在帧或图像的某些区域中，阴影率可以小于每像素一次，而在其它位置，每个像素可以是一次。 可以减少阴影率的示例包括存在运动和照相机散焦的区域，外围模糊的区域，以及一般来说，任何可见度被降低的情况。 通过改变区域的大小，可以在诸如阴影四边形的区域中改变阴影率。

    TECHNIQUES FOR REDUCED PIXEL SHADING
    4.
    发明申请
    TECHNIQUES FOR REDUCED PIXEL SHADING 有权
    减少像素着色的技术

    公开(公告)号：US20150379761A1

    公开(公告)日：2015-12-31

    申请号：US14319472

    申请日：2014-06-30

    申请人： Gabor Liktor ,  Marco Salvi ,  Karthik Vaidyanathan

    发明人： Gabor Liktor ,  Marco Salvi ,  Karthik Vaidyanathan

    IPC分类号： G06T15/20 ,  G06T15/80 ,  G06T11/00 ,  G06T17/10

    CPC分类号： G06T15/80 ,  G06T11/40 ,  G06T15/30

    摘要： Various embodiments are generally directed to techniques for reducing processing demands of shading primitives in rendering a 2D screen image from a 3D model. A device includes a clipping component to clip a visible primitive of a 2D screen image derived from of a 3D model within a first area of the screen image covered by a shading pixel to form a polygon representing an intersection of the first area and the visible primitive; a first interpolation component to interpolate at least one attribute of vertices of the visible primitive to each vertex of the polygon; and a second interpolation component to interpolate color values of the vertices of the polygon to a point within a second area covered by a screen pixel of the screen image, the second area smaller than the first area and at least partly coinciding with the first area. Other embodiments are described and claimed.

    摘要翻译： 各种实施例通常涉及用于在从3D模型渲染2D屏幕图像时减少着色原语的处理需求的技术。 一种设备包括剪切部件，用于剪切由遮蔽像素覆盖的屏幕图像的第一区域内由3D模型导出的2D屏幕图像的可见原始图形，以形成表示第一区域和可见原始图像的交点的多边形 ; 将所述可见原语的顶点的至少一个属性的内插内插到所述多边形的每个顶点的第一插值部件; 以及第二内插分量，以将多边形的顶点的颜色值内插到由屏幕图像的屏幕像素覆盖的第二区域内的点，第二区域小于第一区域，并且至少部分地与第一区域重合。 描述和要求保护其他实施例。

    Analog to digital converter bit width and gain controller for a wireless receiver
    9.
    发明授权
    Analog to digital converter bit width and gain controller for a wireless receiver 有权
    用于无线接收器的模数转换器位宽和增益控制器

    公开(公告)号：US08073085B1

    公开(公告)日：2011-12-06

    申请号：US11825832

    申请日：2007-07-07

    申请人： Karthik Vaidyanathan ,  Partha Sarathy Murali

    发明人： Karthik Vaidyanathan ,  Partha Sarathy Murali

    IPC分类号： H04L27/08

    CPC分类号： H04L27/2647 ,  H04L27/2613

    摘要： A gain controller for a wireless communication system sets the receiver gain during the initial time duration of a preamble, and for each subsequent symbol computes a new gain value, which is applied at the end of each symbol. An analog to digital converter resolution controller sets the resolution of the ADC to a high resolution during a preamble interval and a first symbol interval, and to a comparatively lower resolution thereafter until the end of the frame. When a new zone is entered, the first symbol of the new zone is sampled at a higher resolution than the subsequent symbols.

    摘要翻译： 用于无线通信系统的增益控制器在前导码的初始持续时间期间设置接收机增益，并且对于每个后续符号计算在每个符号的末尾应用的新的增益值。 模数转换器分辨率控制器在前导码间隔和第一符号间隔期间将ADC的分辨率设置为高分辨率，并且之后到相对较低的分辨率直到帧结束。 当输入新区域时，新区域的第一个符号以比后续符号更高的分辨率进行采样。

    Programmable CORDIC Processor with Stage Re-Use
    10.
    发明申请
    Programmable CORDIC Processor with Stage Re-Use 有权
    可编程CORDIC处理器，具有舞台重复使用

    公开(公告)号：US20100138632A1

    公开(公告)日：2010-06-03

    申请号：US12327395

    申请日：2008-12-03

    申请人： Phanimithra Gangalakurti ,  Karthik Vaidyanathan ,  Partha Sarathy Murali ,  InduShekhar Ayyalasomayajula

    发明人： Phanimithra Gangalakurti ,  Karthik Vaidyanathan ,  Partha Sarathy Murali ,  InduShekhar Ayyalasomayajula

    IPC分类号： G06F15/76 ,  G06F7/00

    CPC分类号： G06F7/4818

    摘要： A CORDIC processor has a plurality of stages, each of the stages having a X input, Y input, a sign input, a sign output, an X output, a Y output, a mode control input having a ROTATE or VECTOR value, and a stage number k input, each CORDIC stage having a first shift generating an output by shifting the Y input k times, a second shift generating an output by shifting X input k times, a multiplexer having an output coupled to the sign input when the mode control input is ROTATE and to the sign of the Y input when the mode input is VECTOR, a first multiplier forming the product of the first shift output and the multiplexer output, a second multiplier forming the product of the second shift output and an inverted the multiplexer output, a first adder forming the X output from the sum of the first multiplier output and the X input, and a second adder forming the Y output from the sum of the second multiplier output and the Y input.

    摘要翻译： CORDIC处理器具有多个级，每个级具有X输入，Y输入，符号输入，符号输出，X输出，Y输出，具有ROTATE或VECTOR值的模式控制输入，以及 每个CORDIC级具有通过移位Y输入k次而产生输出的第一移位，通过移位X个输入k次来产生输出的第二移位;当模式控制时，具有耦合到符号输入的输出的多路复用器 当模式输入为VECTOR时，输入为ROTATE和Y输入的符号，形成第一移位输出和多路复用器输出的乘积的第一乘法器，形成第二移位输出和反相多路复用器的乘积的第二乘法器 输出，从第一乘法器输出和X输入的和形成X输出的第一加法器和从第二乘法器输出和Y输入的和形成Y输出的第二加法器。