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公开(公告)号：US07702884B2
公开(公告)日：2010-04-20
申请号：US11147173
申请日：2005-06-08
申请人： Katsuhiro Yoda , Iwao Sugiyama
发明人： Katsuhiro Yoda , Iwao Sugiyama
IPC分类号： G06F15/00
CPC分类号： G06F15/7867
摘要： A semiconductor integrated circuit includes a reconfigurable circuit including a plurality of computing units interconnected in a reconfigurable manner, a processing circuit including at least one of a fixed logic circuit configured to perform predetermined processing and a parameter-defined special-purpose hardware unit configured to change processing specifications according to parameter settings, a network having reconfigurable connections and coupled to the reconfigurable circuit and to the processing circuit, and at least two interfaces each coupled to the network to provide external coupling for the network.
摘要翻译： 一种半导体集成电路包括：包括以可重新配置的方式互连的多个计算单元的可重构电路;处理电路，包括被配置为执行预定处理的固定逻辑电路和被配置为改变的参数定义的专用硬件单元中的至少一个 根据参数设置处理规范，具有可重配置连接并耦合到可重新配置电路和处理电路的网络，以及至少两个接口，每个接口耦合到网络以提供网络的外部耦合。
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公开(公告)号：US20060155969A1
公开(公告)日：2006-07-13
申请号：US11147173
申请日：2005-06-08
申请人： Katsuhiro Yoda , Iwao Sugiyama
发明人： Katsuhiro Yoda , Iwao Sugiyama
IPC分类号： G06F9/44
CPC分类号： G06F15/7867
摘要： A semiconductor integrated circuit includes a reconfigurable circuit including a plurality of computing units interconnected in a reconfigurable manner, a processing circuit including at least one of a fixed logic circuit configured to perform predetermined processing and a parameter-defined special-purpose hardware unit configured to change processing specifications according to parameter settings, a network having reconfigurable connections and coupled to the reconfigurable circuit and to the processing circuit, and at least two interfaces each coupled to the network to provide external coupling for the network.
摘要翻译： 一种半导体集成电路包括：包括以可重新配置的方式互连的多个计算单元的可重构电路;处理电路，包括被配置为执行预定处理的固定逻辑电路和被配置为改变的参数定义的专用硬件单元中的至少一个 根据参数设置处理规范，具有可重配置连接并耦合到可重新配置电路和处理电路的网络，以及至少两个接口，每个接口耦合到网络以提供网络的外部耦合。
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公开(公告)号：US07394755B2
公开(公告)日：2008-07-01
申请号：US10859534
申请日：2004-06-03
IPC分类号： H04J13/00
CPC分类号： H04N21/43615 , H03M13/235 , H03M13/4107 , H04N21/4135 , H04N21/43637
摘要： A semi-fixed circuit has a plurality of flip flops connectable in series, a first selector and a second selector, and is capable of operations of a plurality of kinds of scrambler and the like. The first selector selects any one of an exclusive OR signal of an input signal and a first feedback signal, the first feedback signal and the input signal, and outputting the result to a first flip flop. The second selector is capable of selecting an exclusive OR signal of an output signal of a second flip flop and a second feedback signal, an output signal of the second flip flop and the second feedback signal, and outputting the result to the first selector as the first feedback signal.
摘要翻译： 半固定电路具有可串联连接的多个触发器，第一选择器和第二选择器，并且能够操作多种扰频器等。 第一选择器选择输入信号和第一反馈信号的异或信号，第一反馈信号和输入信号中的任何一个，并将结果输出到第一触发器。 第二选择器能够选择第二触发器和第二反馈信号的输出信号的异或信号，第二触发器的输出信号和第二反馈信号，并将结果输出到第一选择器作为 第一反馈信号。
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公开(公告)号：US20050265556A1
公开(公告)日：2005-12-01
申请号：US10943926
申请日：2004-09-20
申请人： Naoki Odate , Katsuhiro Yoda
发明人： Naoki Odate , Katsuhiro Yoda
CPC分类号： H03M13/09 , H03M13/235 , H03M13/2732 , H03M13/6508 , H03M13/6513 , H03M13/6519
摘要： A signal processing circuit is configured by connecting a plurality of basic circuits connected in series, each of the basic circuits comprising an arithmetic circuit subjecting a first input signal and a second input signal to a signal processing; a first selection circuit outputting the first input signal or an output signal of the arithmetic circuit; and a second selection circuit outputting the second input signal or an output signal of the arithmetic circuit, so as to make it possible to change operations of the circuit as a whole by properly making a selection on which signal should be output with the aid of the first and second selection circuits, and to execute different signal processing on a single circuit depending on the selection.
摘要翻译： 信号处理电路通过连接串联连接的多个基本电路来构成，每个基本电路包括使第一输入信号和第二输入信号经受信号处理的运算电路; 输出所述第一输入信号或所述运算电路的输出信号的第一选择电路; 以及输出第二输入信号或运算电路的输出信号的第二选择电路，以便通过适当地选择应当输出哪个信号来使得可以整体地改变电路的操作 第一和第二选择电路，并且根据选择在单个电路上执行不同的信号处理。
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公开(公告)号：US07680282B2
公开(公告)日：2010-03-16
申请号：US10943926
申请日：2004-09-20
申请人： Naoki Odate , Katsuhiro Yoda
发明人： Naoki Odate , Katsuhiro Yoda
IPC分类号： H04L9/00
CPC分类号： H03M13/09 , H03M13/235 , H03M13/2732 , H03M13/6508 , H03M13/6513 , H03M13/6519
摘要： A signal processing circuit is configured by connecting a plurality of basic circuits connected in series, each of the basic circuits comprising an arithmetic circuit subjecting a first input signal and a second input signal to a signal processing; a first selection circuit outputting the first input signal or an output signal of the arithmetic circuit; and a second selection circuit outputting the second input signal or an output signal of the arithmetic circuit, so as to make it possible to change operations of the circuit as a whole by properly making a selection on which signal should be output with the aid of the first and second selection circuits, and to execute different signal processing on a single circuit depending on the selection.
摘要翻译： 信号处理电路通过连接串联连接的多个基本电路来构成，每个基本电路包括使第一输入信号和第二输入信号经受信号处理的运算电路; 输出所述第一输入信号或所述运算电路的输出信号的第一选择电路; 以及输出第二输入信号或运算电路的输出信号的第二选择电路，以便通过适当地选择应当输出哪个信号来使得可以整体地改变电路的操作 第一和第二选择电路，并且根据选择在单个电路上执行不同的信号处理。
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公开(公告)号：US07584317B2
公开(公告)日：2009-09-01
申请号：US11889484
申请日：2007-08-14
申请人： Yuki Sakai , Katsuhiro Yoda
发明人： Yuki Sakai , Katsuhiro Yoda
摘要： A protocol conversion circuit performing a protocol conversion between a preceding stage circuit and a succeeding stage circuit includes a data storing unit storing input data from the preceding stage circuit, an output enable signal generating unit generating an output enable signal outputting data stored in the data storing unit to the succeeding stage circuit by using one or more parameters for the protocol conversion which are externally fed and can take a different value each time interval externally specified, and an address specifying unit specifying an address for read of an output data for the data storing unit based on the output enable signal.
摘要翻译： 执行前级电路和后级电路之间的协议转换的协议转换电路包括：存储来自前一级电路的输入数据的数据存储单元;输出使能信号生成单元，生成输出使能信号，输出存储在数据存储器 通过使用外部馈送的协议转换的一个或多个参数，并且可以在外部指定的每个时间间隔获取不同的值，以及指定用于读取用于数据存储的输出数据的地址的地址指定单元到后级电路 基于输出使能信号的单位。
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公开(公告)号：US20080040521A1
公开(公告)日：2008-02-14
申请号：US11889484
申请日：2007-08-14
申请人： Yuki Sakai , Katsuhiro Yoda
发明人： Yuki Sakai , Katsuhiro Yoda
摘要： A protocol conversion circuit performing a protocol conversion between a preceding stage circuit and a succeeding stage circuit includes a data storing unit storing input data from the preceding stage circuit, an output enable signal generating unit generating an output enable signal outputting data stored in the data storing unit to the succeeding stage circuit by using one or more parameters for the protocol conversion which are externally fed and can take a different value each time interval externally specified, and an address specifying unit specifying an address for read of an output data for the data storing unit based on the output enable signal.
摘要翻译： 执行前级电路和后级电路之间的协议转换的协议转换电路包括：存储来自前一级电路的输入数据的数据存储单元;输出使能信号生成单元，生成输出使能信号，输出存储在数据存储器 通过使用外部馈送的协议转换的一个或多个参数，并且可以在外部指定的每个时间间隔获取不同的值，以及指定用于读取用于数据存储的输出数据的地址的地址指定单元到后级电路的单元 基于输出使能信号的单位。
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公开(公告)号：US20070008907A1
公开(公告)日：2007-01-11
申请号：US11360661
申请日：2006-02-24
申请人： Naoki Odate , Katsuhiro Yoda , Seiichi Nishijima , Kazuhiko Shoji
发明人： Naoki Odate , Katsuhiro Yoda , Seiichi Nishijima , Kazuhiko Shoji
IPC分类号： H04L12/28
CPC分类号： G06F15/7867
摘要： A reconfigurable LSI which can actualize a plurality of functions by reconfiguration based on configuration information, comprises at least a plurality of arithmetic processing modules, has state information for indicating the transition of the function from a previous state to a next state, transition condition information for indicating the condition for transitioning from the previous state to the next state, and output information for switching the connection between the arithmetic processing module corresponding to the transition condition and the data network connected to the arithmetic processing module, and has a reconfiguration control circuit which transmits the output information corresponding to the next state to a selector for switching between the arithmetic processing module and the data network when the conditions for transition are received from the arithmetic processing module and matches the condition of the transition condition information.
摘要翻译： 可以通过基于配置信息的重构来实现多个功能的可重构LSI包括至少多个算术处理模块，具有用于指示功能从先前状态到下一状态的转换的状态信息，用于 指示从先前状态转换到下一状态的条件，以及用于切换与转换条件相对应的运算处理模块与连接到算术处理模块的数据网络之间的连接的输出信息，并且具有发送 当从算术处理模块接收到转换条件并与转换条件信息的条件匹配时，将与下一状态相对应的输出信息提供给选择器，用于在算术处理模块和数据网络之间进行切换。
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公开(公告)号：US20050094804A1
公开(公告)日：2005-05-05
申请号：US10859534
申请日：2004-06-03
CPC分类号： H04N21/43615 , H03M13/235 , H03M13/4107 , H04N21/4135 , H04N21/43637
摘要： A semi-fixed circuit has a plurality of flip flops connectable in series, a first selector and a second selector, and is capable of operations of a plurality of kinds of scrambler and the like. The first selector selects any one of an exclusive OR signal of an input signal and a first feedback signal, the first feedback signal and the input signal, and outputting the result to a first flip flop. The second selector is capable of selecting an exclusive OR signal of an output signal of a second flip flop and a second feedback signal, an output signal of the second flip flop and the second feedback signal, and outputting the result to the first selector as the first feedback signal.
摘要翻译： 半固定电路具有可串联连接的多个触发器，第一选择器和第二选择器，并且能够操作多种扰频器等。 第一选择器选择输入信号和第一反馈信号的异或信号，第一反馈信号和输入信号中的任何一个，并将结果输出到第一触发器。 第二选择器能够选择第二触发器和第二反馈信号的输出信号的异或信号，第二触发器的输出信号和第二反馈信号，并将结果输出到第一选择器作为 第一反馈信号。
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