公开(公告)号：US07202846B2

公开(公告)日：2007-04-10

申请号：US10440077

申请日：2003-05-15

申请人： Kazuhiro Maeda ,  Sachio Tsujino ,  Keiji Takahashi ,  Hajime Washio

发明人： Kazuhiro Maeda ,  Sachio Tsujino ,  Keiji Takahashi ,  Hajime Washio

IPC分类号： G09G3/36

CPC分类号： G09G3/3688 ,  G09G2310/0294 ,  G09G2330/021 ,  G09G2340/0421

摘要： A data signal line drive circuit is provided with: a shift register belonging to a system, whose stages correspond to respective sampling units for driving odd-number-th data signal lines; and a shift register belonging to another system, whose stages correspond to respective sampling units for driving even-number-th data signal lines. On the occasion of low-resolution mode, only either of the shift registers is operated, and in accordance with the outputs from the respective stages of the shift register which has been operated, timing signals, which are supplied to the sampling units corresponding to the stages of both shift registers, are generated. With this arrangement, even if one of input signals each having different signal line resolution is inputted, a signal line drive circuit which consumes a small amount of electric power can be realized, while it is possible to specify the timings of the operation of signal line drive sections for driving signal lines, in accordance with the input signal.

摘要翻译： 数据信号线驱动电路具有：属于系统的移位寄存器，其级对应于用于驱动奇数数据信号线的相应采样单元; 以及属于另一系统的移位寄存器，其级对应于用于驱动第二数据信号线的相应采样单元。 在低分辨率模式的情况下，仅移动寄存器中的任一个被操作，并且根据已经被操作的移位寄存器的各个级的输出，定时信号被提供给对应于 生成两个移位寄存器的阶段。 通过这样的配置，即使输入信号线分辨率不同的输入信号之一，也可以实现消耗少量电力的信号线驱动电路，同时可以规定信号线的动作时序 用于驱动信号线的驱动部分，根据输入信号。

公开(公告)号：US20080036753A1

公开(公告)日：2008-02-14

申请号：US11882533

申请日：2007-08-02

申请人： Hajime Washio ,  Yasuyoshi Kaise ,  Sachio Tsujino ,  Kazuhiro Maeda ,  Keiji Takahashi ,  Yasushi Kubota ,  Toshiya Aoki

发明人： Hajime Washio ,  Yasuyoshi Kaise ,  Sachio Tsujino ,  Kazuhiro Maeda ,  Keiji Takahashi ,  Yasushi Kubota ,  Toshiya Aoki

IPC分类号： G06F3/038

CPC分类号： G09G3/3688 ,  G09G3/3614 ,  G09G3/3648 ,  G09G3/3666 ,  G09G3/3677 ,  G09G2310/0213 ,  G09G2310/0232 ,  G09G2310/027 ,  G09G2310/0283 ,  G09G2310/0297 ,  G09G2310/04 ,  G09G2320/0214 ,  G09G2320/10 ,  G09G2330/021

摘要： An example control signal generating circuit CTL for controlling the writing into pixels PIX instructs a data signal line drive circuit SD2, which is for driving pixels in a non-display area, to write a voltage VB or a voltage VW which are for non-displaying, not only in the first frame but also once in a predetermined number of frames. In other words, the pixels in the display area are refreshed at intervals longer than those in the case of refreshing the pixels in each frame. Thus, even if the mobility of an active element is high and the leak current on the occasion of OFF-state is large, or even if a large amount of electric charge is accumulated because of the photoelectric effect due to the use of a backlight, it is possible to prevent unnecessary displaying on the display area, which is caused because the writing into the pixels in the display area influences on the pixels in the non-display area, and hence it is possible to improve the quality of partial displaying, while restraining the power consumption.

摘要翻译： 用于控制写入像素PIX的示例性控制信号发生电路CTL指示用于驱动非显示区域中的像素的数据信号线驱动电路SD 2写入用于非显示区域的电压VB或电压VW， 不仅在第一帧中显示，而且在预定数量的帧中显示一次。 换句话说，显示区域中的像素以比刷新每帧中的像素的情况更长的间隔更新。 因此，即使有源元件的迁移率高，关断状态下的漏电流大，或者即使由于使用背光导致的光电效应而累积大量的电荷， 可以防止由于对显示区域中的像素的写入而影响非显示区域中的像素而导致的显示区域的不必要的显示，因此可以提高部分显示的质量，同时 限制功耗。

公开(公告)号：US08130216B2

公开(公告)日：2012-03-06

申请号：US11882533

申请日：2007-08-02

申请人： Hajime Washio ,  Yasuyoshi Kaise ,  Sachio Tsujino ,  Kazuhiro Maeda ,  Keiji Takahashi ,  Yasushi Kubota ,  Toshiya Aoki

发明人： Hajime Washio ,  Yasuyoshi Kaise ,  Sachio Tsujino ,  Kazuhiro Maeda ,  Keiji Takahashi ,  Yasushi Kubota ,  Toshiya Aoki

IPC分类号： G09G5/00

CPC分类号： G09G3/3688 ,  G09G3/3614 ,  G09G3/3648 ,  G09G3/3666 ,  G09G3/3677 ,  G09G2310/0213 ,  G09G2310/0232 ,  G09G2310/027 ,  G09G2310/0283 ,  G09G2310/0297 ,  G09G2310/04 ,  G09G2320/0214 ,  G09G2320/10 ,  G09G2330/021

摘要： An example control signal generating circuit CTL for controlling the writing into pixels PIX instructs a data signal line drive circuit SD2, which is for driving pixels in a non-display area, to write a voltage VB or a voltage VW which are for non-displaying, not only in the first frame but also once in a predetermined number of frames. In other words, the pixels in the display area are refreshed at intervals longer than those in the case of refreshing the pixels in each frame. Thus, even if the mobility of an active element is high and the leak current on the occasion of OFF-state is large, or even if a large amount of electric charge is accumulated because of the photoelectric effect due to the use of a backlight, it is possible to prevent unnecessary displaying on the display area, which is caused because the writing into the pixels in the display area influences on the pixels in the non-display area, and hence it is possible to improve the quality of partial displaying, while restraining the power consumption.

摘要翻译： 用于控制写入像素PIX的示例性控制信号发生电路CTL指示用于驱动非显示区域中的像素的数据信号线驱动电路SD2写入用于不显示的电压VB或电压VW ，不仅在第一帧中，而且在预定数量的帧中也是一次。 换句话说，显示区域中的像素以比刷新每帧中的像素的情况更长的间隔更新。 因此，即使有源元件的迁移率高，关断状态下的漏电流大，或者即使由于使用背光导致的光电效应而累积大量的电荷， 可以防止由于对显示区域中的像素的写入而影响非显示区域中的像素而导致的显示区域的不必要的显示，因此可以提高部分显示的质量，同时 限制功耗。

公开(公告)号：US07333096B2

公开(公告)日：2008-02-19

申请号：US10316193

申请日：2002-12-11

申请人： Hajime Washio ,  Yasuyoshi Kaise ,  Sachio Tsujino ,  Kazuhiro Maeda ,  Keiji Takahashi ,  Yasushi Kubota ,  Toshiya Aoki

发明人： Hajime Washio ,  Yasuyoshi Kaise ,  Sachio Tsujino ,  Kazuhiro Maeda ,  Keiji Takahashi ,  Yasushi Kubota ,  Toshiya Aoki

IPC分类号： G09G5/00 ,  G09G3/36

CPC分类号： G09G3/3688 ,  G09G3/3614 ,  G09G3/3648 ,  G09G3/3666 ,  G09G3/3677 ,  G09G2310/0213 ,  G09G2310/0232 ,  G09G2310/027 ,  G09G2310/0283 ,  G09G2310/0297 ,  G09G2310/04 ,  G09G2320/0214 ,  G09G2320/10 ,  G09G2330/021

摘要： A control signal generating circuit CTL for controlling the writing into pixels PIX instructs a data signal line drive circuit SD2, which is for driving pixels in a non-display area, to write a voltage VB or a voltage VW which are for non-displaying, not only in the first frame but also once in a predetermined number of frames. In other words, the pixels in the display area is refreshed at intervals longer than those in the case of refreshing the pixels in each frame. Thus, even if the mobility of an active element is high and the leak current on the occasion of OFF-state is large, or even if a large amount of electric charge is accumulated because of the photoelectric effect due to the use of a backlight, it is possible to prevent unnecessary displaying on the display area, which is caused because the writing into the pixels in the display area influences on the pixels in the non-display area, and hence it is possible to improve the quality of partial displaying, while restraining the power consumption.

摘要翻译： 用于控制向像素PIX写入的控制信号发生电路CTL指示用于驱动非显示区域中的像素的数据信号线驱动电路SD 2写入用于不显示的电压VB或电压VW ，不仅在第一帧中，而且在预定数量的帧中也是一次。 换句话说，显示区域中的像素以比刷新每帧中的像素的情况更长的间隔更新。 因此，即使有源元件的迁移率高，关断状态下的漏电流大，或者即使由于使用背光导致的光电效应而累积大量的电荷， 可以防止由于对显示区域中的像素的写入而影响非显示区域中的像素而导致的显示区域的不必要的显示，因此可以提高部分显示的质量，同时 限制功耗。

公开(公告)号：US07652652B2

公开(公告)日：2010-01-26

申请号：US10705775

申请日：2003-11-12

申请人： Kazuhiro Maeda ,  Sachio Tsujino ,  Hajime Washio ,  Yuhji Asoh

发明人： Kazuhiro Maeda ,  Sachio Tsujino ,  Hajime Washio ,  Yuhji Asoh

IPC分类号： G09G3/36

CPC分类号： G09G3/3685 ,  G09G3/20 ,  G09G3/2011 ,  G09G2310/0297

摘要： The data signal line driving circuit of the present invention is arranged so that data signal line groups, each of which is made up of two data signal lines sequentially disposed, are connected to two video signal lines, each of which allows a two-phased video signal to be forwarded. A shift register SR, a drive switching circuit, and a waveform shaping circuit, that constitute a video signal fetching section, collect the data signal line groups via the two video signal lines as a single block. At this time, the data signal lines are respectively driven so as to fetch the video signal from the video signal lines into the data signal lines of the data signal line groups in each block. Thus, in performing multiphase development, it is possible to provide the data signal line driving circuit which can reduce power consumption in low resolution driving compared with a case of high resolution driving.

摘要翻译： 本发明的数据信号线驱动电路被布置成使得由两条数据信号线构成的数据信号线组连接到两条视频信号线，每条视频信号线允许两相视频 信号被转发。 构成视频信号取出部的移位寄存器SR，驱动切换电路以及波形整形电路通过两个视频信号线收集数据信号线组作为单个块。 此时，分别驱动数据信号线，以将视频信号从视频信号线提取到每个块中的数据信号线组的数据信号线中。 因此，在执行多相显影时，与高分辨率驱动的情况相比，可以提供能够降低分辨率驱动中的功耗的数据信号线驱动电路。

公开(公告)号：US07733321B2

公开(公告)日：2010-06-08

申请号：US11543219

申请日：2006-10-05

申请人： Shunsuke Hayashi ,  Seijirou Gyouten ,  Hajime Washio ,  Eiji Matsuda ,  Sachio Tsujino ,  Yuichiro Murakami

发明人： Shunsuke Hayashi ,  Seijirou Gyouten ,  Hajime Washio ,  Eiji Matsuda ,  Sachio Tsujino ,  Yuichiro Murakami

IPC分类号： G09G3/36

CPC分类号： G11C19/00 ,  G09G3/20 ,  G09G2300/08 ,  G09G2310/0267 ,  G09G2310/0275 ,  G09G2310/0283 ,  G09G2310/0286 ,  G09G2310/08 ,  G11C19/28

摘要： A shift register includes plural stages of flip-flops. The last-stage flip-flop Fn and the flip-flop Fn−1 that is the preceding flip-flop thereof are reset by inputting thereto an output signal from the last-stage flip-flop. A delaying means is provided, between an output terminal Q of the last-stage flip-flop for outputting the output signal and an input terminal R of the last-stage flip-flop for receiving the output signal, for delaying an input of the output signal to the input terminal R. The flip-flop Fn is reset at same time or after the preceding flip-flop Fn−1 is reset. With this arrangement, it is possible to prevent malfunctions of circuits due to a failure to reset the flip-flops.

摘要翻译： 移位寄存器包括多级触发器。 作为其前一触发器的最后级触发器Fn和触发器Fn-1通过向其输入来自最后级触发器的输出信号而被复位。 在用于输出输出信号的最后级触发器的输出端Q和用于接收输出信号的最后级触发器的输入端R之间提供延迟装置，用于延迟输出的输入 信号到输入端R.触发器Fn在同一时间或在先前的触发器Fn-1复位之后复位。 通过这种布置，可以防止由于不能重置触发器而引起的电路故障。

公开(公告)号：US20070242021A1

公开(公告)日：2007-10-18

申请号：US11812461

申请日：2007-06-19

申请人： Yuhichiroh Murakami ,  Seijirou Gyouten ,  Hajime Washio ,  Eiji Matsuda ,  Sachio Tsujino ,  Shunsuke Hayashi

发明人： Yuhichiroh Murakami ,  Seijirou Gyouten ,  Hajime Washio ,  Eiji Matsuda ,  Sachio Tsujino ,  Shunsuke Hayashi

IPC分类号： H03K19/0175

CPC分类号： G09G3/3611 ,  G09G2300/0408 ,  G09G2310/0289 ,  H03K19/0013 ,  H03K19/018521

摘要： A level shift circuit includes first and second level shifters which respectively output first and second output signals that are produced by level shifting two kinds of input clock signals whose high level periods do not overlap. The level shift circuit also includes control transistors and control lines which, together, prevent a feedthrough current from flowing into the second level shifter when the first output signal is high level, and prevent a feedthrough current from flowing into the first level shifter when the second output signal is high level, so as to suspend the level shift operation of the first and second level shifters. With the level shift circuit, power consumption during a specific time period in a non-active period of the clock signal can be eliminated, where the specific time period of one clock signal is the active period of the other clock signal.

公开(公告)号：US20050175138A1

公开(公告)日：2005-08-11

申请号：US11044003

申请日：2005-01-28

申请人： Eiji Matsuda ,  Yuhichiroh Murakami ,  Sachio Tsujino ,  Hajime Washio

发明人： Eiji Matsuda ,  Yuhichiroh Murakami ,  Sachio Tsujino ,  Hajime Washio

IPC分类号： G02F1/133 ,  G09G3/20 ,  G09G3/36 ,  G11C19/00 ,  G11C19/28 ,  H03K17/693

CPC分类号： G09G3/3688 ,  G11C19/00 ,  G11C19/28

摘要： In a shift register of the present invention, each of flip-flops has a phase difference detection section and a waveform timing forming section as a malfunction prevention circuit. The phase difference detection section detects an overlapping waveform caused by a phase difference between clock signals SCK and SCKB, and generates an output signal A (A1, A2, . . . ) from which the overlapping portions are removed. The waveform timing forming section outputs an output signal X (X1, X2, . . . ) obtained by extracting a period when the output signal A (A1, A2, . . . ) generated in a corresponding phase difference detection section is High, when an output signal Q (Q1, Q2, . . . ) from a corresponding flip-flop is High. The output signal X (X1, X2, . . . ) sets a flip-flop in a following stage. According to the above arrangement, it is possible to realize a shift register which does not malfunction and functions properly even in cases where two clock signals SCK and SCKB inputted to the shift register and having different phases from each other are out of phase. It is also possible to realize a display device having the shift register.

摘要翻译： 在本发明的移位寄存器中，每个触发器具有作为故障防止电路的相位差检测部分和波形定时形成部分。 相位差检测部分检测由时钟信号SCK和SCKB之间的相位差引起的重叠波形，并且生成从其重叠​​部分被去除的输出信号A（A 1，A 2，...）。 波形定时形成部输出通过提取在对应的相位差检测部中产生的输出信号A（A 1，A 2，...）的周期而获得的输出信号X（X 1，X 2，...） 当来自相应触发器的输出信号Q（Q 1，Q 2，...）为高时，为高电平。 输出信号X（X 1，X 2，...）在下一阶段设置触发器。 根据上述结构，即使在输入到移位寄存器的两个时钟信号SCK，SCKB彼此相位不同的情况下也可以实现不发生故障的功能，也能正常工作的移位寄存器。 也可以实现具有移位寄存器的显示装置。

公开(公告)号：US07688302B2

公开(公告)日：2010-03-30

申请号：US11543218

申请日：2006-10-05

申请人： Shunsuke Hayashi ,  Seijirou Gyouten ,  Hajime Washio ,  Eiji Matsuda ,  Sachio Tsujino ,  Yuichiro Murakami

发明人： Shunsuke Hayashi ,  Seijirou Gyouten ,  Hajime Washio ,  Eiji Matsuda ,  Sachio Tsujino ,  Yuichiro Murakami

IPC分类号： G09G3/36

CPC分类号： G11C19/00 ,  G09G3/20 ,  G09G2300/08 ,  G09G2310/0267 ,  G09G2310/0275 ,  G09G2310/0283 ,  G09G2310/0286 ,  G09G2310/08 ,  G11C19/28

摘要： A shift register includes plural stages of flip-flops. The last-stage flip-flop Fn and the flip-flop Fn−1 that is the preceding flip-flop thereof are reset by inputting thereto an output signal from the last-stage flip-flop. A delaying means is provided, between an output terminal Q of the last-stage flip-flop for outputting the output signal and an input terminal R of the last-stage flip-flop for receiving the output signal, for delaying an input of the output signal to the input terminal R. The flip-flop Fn is reset at same time or after the preceding flip-flop Fn−1 is reset. With this arrangement, it is possible to prevent malfunctions of circuits due to a failure to reset the flip-flops.

公开(公告)号：US07505022B2

公开(公告)日：2009-03-17

申请号：US11044003

申请日：2005-01-28

申请人： Eiji Matsuda ,  Yuhichiroh Murakami ,  Sachio Tsujino ,  Hajime Washio

发明人： Eiji Matsuda ,  Yuhichiroh Murakami ,  Sachio Tsujino ,  Hajime Washio

IPC分类号： G09G3/36

CPC分类号： G09G3/3688 ,  G11C19/00 ,  G11C19/28

摘要： In a shift register of the present invention, each of flip-flops has a phase difference detection section and a waveform timing forming section as a malfunction prevention circuit. The phase difference detection section detects an overlapping waveform caused by a phase difference between clock signals SCK and SCKB, and generates an output signal A (A1, A2, . . . ) from which the overlapping portions are removed. The waveform timing forming section outputs an output signal X (X1, X2, . . . ) obtained by extracting a period when the output signal A (A1, A2, . . . ) generated in a corresponding phase difference detection section is High, when an output signal Q (Q1, Q2, . . . ) from a corresponding flip-flop is High. The output signal X (X1, X2, . . . ) sets a flip-flop in a following stage. According to the above arrangement, it is possible to realize a shift register which does not malfunction and functions properly even in cases where two clock signals SCK and SCKB inputted to the shift register and having different phases from each other are out of phase. It is also possible to realize a display device having the shift register.

摘要翻译： 在本发明的移位寄存器中，每个触发器具有作为故障防止电路的相位差检测部分和波形定时形成部分。 相位差检测部分检测由时钟信号SCK和SCKB之间的相位差引起的重叠波形，并产生从其重叠部分被去除的输出信号A（A1，A2 ...）。 波形定时形成部输出通过提取在相应的相位差检测部中产生的输出信号A（A1，A2 ......）的高电平的期间而获得的输出信号X（X1，X2 ...），当 来自相应触发器的输出信号Q（Q1，Q2 ...）为高。 输出信号X（X1，X2，...）在下一阶段设置触发器。 根据上述结构，即使在输入到移位寄存器的两个时钟信号SCK，SCKB彼此相位不同的情况下也可以实现不发生故障的功能，也能正常工作的移位寄存器。 也可以实现具有移位寄存器的显示装置。