公开(公告)号：US07093215B2

公开(公告)日：2006-08-15

申请号：US10751892

申请日：2004-01-07

申请人： Yasuyuki Sahara ,  Katsuhiro Ootani ,  Kazuhisa Nakata ,  Shinsaku Sekido

发明人： Yasuyuki Sahara ,  Katsuhiro Ootani ,  Kazuhisa Nakata ,  Shinsaku Sekido

IPC分类号： G06F17/50

CPC分类号： G06F17/5045 ,  H01L27/0207

摘要： An inventive semiconductor circuit device includes an N-well and a P-well. The N-well is provided with PMIS active areas surrounded by a trench isolation, and the P-well is provided with NMIS active areas surrounded by the trench isolation. The PMIS active areas are each provided with a gate of a P-channel transistor, and the NMIS active areas are each provided with a gate of an N-channel transistor. A layout is designed such that a distance Dpn between the NMIS active areas and the PMIS active areas in a Y-direction substantially becomes a fixed value. Thus, trench isolation stresses applied from the trench isolations to channel regions under the gates become uniform for respective transistors, resulting in an improvement in accuracy of circuit simulation.

摘要翻译： 本发明的半导体电路器件包括N阱和P阱。 N阱具有被沟槽隔离环绕的PMIS有源区，并且P阱具有由沟槽隔离包围的NMIS有源区。 PMIS有源区域各自设置有P沟道晶体管的栅极，并且NMIS有源区域各自设置有N沟道晶体管的栅极。 设计布局，使得NMIS有效区域与Y方向上的PMIS有效区域之间的距离Dpn基本上变为固定值。 因此，从沟槽隔离施加到栅极下方的沟道区的沟槽隔离应力对于各个晶体管而变得均匀，导致电路仿真精度的提高。

公开(公告)号：US06963115B2

公开(公告)日：2005-11-08

申请号：US10656199

申请日：2003-09-08

申请人： Kazuhisa Nakata ,  Katsuhiro Ootani ,  Yasuyuki Sahara ,  Shinsaku Sekido

发明人： Kazuhisa Nakata ,  Katsuhiro Ootani ,  Yasuyuki Sahara ,  Shinsaku Sekido

IPC分类号： H01L27/08 ,  H01L21/82 ,  H01L21/8234 ,  H01L21/8238 ,  H01L27/02 ,  H01L27/088 ,  H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC分类号： H01L21/823828 ,  H01L21/823437 ,  H01L27/0203

摘要： Gates of pMISFETs which need high current driving capability are high-driving-capability gates placed in discontinuous active regions or high-driving-capability gates disposed in two-input active regions. Gate of pMISFETs which do not need high current driving capability are normal gates arranged in continuous active regions. Since the high-driving-capability gates are provided in the discontinuous active regions or the two-input active regions, pMISFETs with high driving capability is achieved by utilizing light holes created due to a lattice distortion.

摘要翻译： 需要高电流驱动能力的pMISFET的栅极是放置在不连续有源区域中的高驱动能力门或设置在双输入有源区域中的高驱动能力门。 不需要高电流驱动能力的pMISFET的栅极是布置在连续有源区域中的常规栅极。 由于高驱动能力门设置在不连续的有源区域或双输入有源区域中，所以通过利用由于晶格畸变而产生的光孔来实现具有高驱动能力的pMISFET。

公开(公告)号：US20060259881A1

公开(公告)日：2006-11-16

申请号：US11488050

申请日：2006-07-18

申请人： Yasuyuki Sahara ,  Katsuhiro Ootani ,  Kazuhisa Nakata ,  Shinsaku Sekido

发明人： Yasuyuki Sahara ,  Katsuhiro Ootani ,  Kazuhisa Nakata ,  Shinsaku Sekido

IPC分类号： G06F17/50 ,  H01L31/00

CPC分类号： G06F17/5045 ,  H01L27/0207

摘要： An inventive semiconductor circuit device includes an N-well and a P-well. The N-well is provided with PMIS active areas surrounded by a trench isolation, and the P-well is provided with NMIS active areas surrounded by the trench isolation. The PMIS active areas are each provided with a gate of a P-channel transistor, and the NMIS active areas are each provided with a gate of an N-channel transistor. A layout is designed such that a distance Dpn between the NMIS active areas and the PMIS active areas in a Y-direction substantially becomes a fixed value. Thus, trench isolation stresses applied from the trench isolations to channel regions under the gates become uniform for respective transistors, resulting in an improvement in accuracy of circuit simulation.

公开(公告)号：US07562327B2

公开(公告)日：2009-07-14

申请号：US11591452

申请日：2006-11-02

申请人： Shinsaku Sekido ,  Kyoji Yamashita ,  Katsuhiro Ootani ,  Yasuyuki Sahara ,  Daisaku Ikoma

发明人： Shinsaku Sekido ,  Kyoji Yamashita ,  Katsuhiro Ootani ,  Yasuyuki Sahara ,  Daisaku Ikoma

IPC分类号： G06F17/50

CPC分类号： H01L27/0207 ,  H01L21/823878 ,  H01L21/823892 ,  H01L29/41758

摘要： In a cell comprising an N well and a P well, a distance SP04 from a center line of a contact N-type region to an N well end of the N well is set to be a distance which causes a transistor not to be affected by resist. A distance from a well boundary to the center line of the contact N-type region is equal to SP04. A design on the P well is similar to that on the N well. Thereby, modeling of the transistor in the cell can be performed, taking into consideration an influence from resist in one direction. Also, by fabricating a cell array which satisfies the above-described conditions, design accuracy can be improved.

摘要翻译： 在包括N阱和P阱的单元中，从接触N型区域的中心线到N阱的N阱端的距离SP04被设定为使晶体管不受影响的距离 抗。 从阱边界到接触N型区域的中心线的距离等于SP04。 P井的设计与N井相似。 因此，考虑到在一个方向上的抗蚀剂的影响，可以对单元中的晶体管进行建模。 此外，通过制造满足上述条件的单元阵列，可以提高设计精度。

公开(公告)号：US20070141766A1

公开(公告)日：2007-06-21

申请号：US11591452

申请日：2006-11-02

申请人： Shinsaku Sekido ,  Kyoji Yamashita ,  Katsuhiro Ootani ,  Yasuyuki Sahara ,  Daisaku Ikoma

发明人： Shinsaku Sekido ,  Kyoji Yamashita ,  Katsuhiro Ootani ,  Yasuyuki Sahara ,  Daisaku Ikoma

IPC分类号： H01L21/84

CPC分类号： H01L27/0207 ,  H01L21/823878 ,  H01L21/823892 ,  H01L29/41758

摘要： In a cell comprising an N well and a P well, a distance SP04 from a center line of a contact N-type region to an N well end of the N well is set to be a distance which causes a transistor not to be affected by resist. A distance from a well boundary to the center line of the contact N-type region is equal to SP04. A design on the P well is similar to that on the N well. Thereby, modeling of the transistor in the cell can be performed, taking into consideration an influence from resist in one direction. Also, by fabricating a cell array which satisfies the above-described conditions, design accuracy can be improved.

摘要翻译： 在包括N阱和P阱的单元中，从接触N型区域的中心线到N阱的N阱端的距离SP 04被设定为使晶体管不受影响的距离 抗拒。 从触点N型区域的阱边界到中心线的距离等于SP 04。 P井的设计与N井相似。 因此，考虑到在一个方向上的抗蚀剂的影响，可以对单元中的晶体管进行建模。 此外，通过制造满足上述条件的单元阵列，可以提高设计精度。