公开(公告)号：US20120103675A1

公开(公告)日：2012-05-03

申请号：US13280734

申请日：2011-10-25

申请人： Kazunari KIMURA ,  Junichi NAKAMURA ,  Takeshi KIJIMA ,  Isao ABE ,  Takahiro SUZUKI ,  Toshiaki ARAKI

发明人： Kazunari KIMURA ,  Junichi NAKAMURA ,  Takeshi KIJIMA ,  Isao ABE ,  Takahiro SUZUKI ,  Toshiaki ARAKI

IPC分类号： H05K1/11 ,  H05K3/42 ,  H05K1/16

CPC分类号： H05K3/4061 ,  H01P1/20345 ,  H05K3/4629 ,  Y10T29/49165

摘要： A laminated electronic device comprises two or more wiring layers including a first wiring layer and a second wiring layer, an insulating layer interposed between the first wiring layer and second wiring layer, and a through conductor extending through the insulating layer for electrically connecting a first conductor disposed on the first wiring layer to a second conductor disposed on the second wiring layer. The through conductor includes divergent sections at both ends, which have a diameter gradually increased toward the first conductor or second conductor.

摘要翻译： 层叠电子器件包括两个或更多个布线层，包括第一布线层和第二布线层，插入在第一布线层和第二布线层之间的绝缘层，以及穿过绝缘层的贯通导体，用于将第一布线 布置在第一布线层上的布置在第二布线层上的第二导体。 贯通导体包括两端的发散部分，其具有朝向第一导体或第二导体逐渐增加的直径。

公开(公告)号：US20100229139A1

公开(公告)日：2010-09-09

申请号：US12702129

申请日：2010-02-08

申请人： Miyako KITAOKA ,  Kazunari KIMURA

发明人： Miyako KITAOKA ,  Kazunari KIMURA

IPC分类号： G06F17/50

CPC分类号： G06F17/5081 ,  G06F2217/12 ,  Y02P90/265

摘要： An extraction unit extracts a metal pattern constituting a semiconductor integrated circuit from layout data. A setting unit sets up a region including the metal pattern extracted by the extraction unit. An evaluation unit calculates the metal coverage rate of the region and to evaluate whether the metal coverage rate is equal to or more than a predetermined value. An insertion unit inserts a dummy metal pattern into the region when the metal coverage rate is evaluated as a value smaller than the predetermined value by the evaluation unit.

摘要翻译： 提取单元从布局数据中提取构成半导体集成电路的金属图案。 设置单元设置包括由提取单元提取的金属图案的区域。 评估单元计算该区域的金属覆盖率并评估金属覆盖率是否等于或大于预定值。 当通过评估单元将金属覆盖率评估为小于预定值的值时，插入单元将虚设金属图案插入到该区域中。

公开(公告)号：US20130074027A1

公开(公告)日：2013-03-21

申请号：US13422236

申请日：2012-03-16

申请人： Kazunari KIMURA

发明人： Kazunari KIMURA

IPC分类号： G06F17/50

CPC分类号： G06F17/5077

摘要： A designing device for a semiconductor integrated circuit of an embodiment includes a low-order hierarchy wiring design portion configured to design a first wiring; and a high-order hierarchy wiring design portion configured to design a second wiring. The low-order hierarchy wiring design portion divides the first functional block into a plurality of small regions, calculates a number of wiring layers required for wiring in the functional block for each of the plurality of small regions and sets the number as the number of low-order hierarchy wiring layers, sets wiring layers in the number of the low-order hierarchy wiring layers from the wiring layer located on the lowermost part as a low-order hierarchy wiring region for each of the plurality of small regions, and places the first wiring in the low-order hierarchy wiring region.

摘要翻译： 实施例的半导体集成电路的设计装置包括被配置为设计第一布线的低阶层布线设计部分; 以及配置为设计第二布线的高阶层布线设计部分。 低级布线设计部将第一功能块分割为多个小区域，计算多个小区域中的每一个的功能块中布线所需的布线层数，并将该数量设定为低 将位于最下部的布线层的低层布线层的数量的布线层设置为多个小区域中的每一个的低层布线区域的布线层，并且将第一层布线层 布线在低层布线区域。