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    Method and device for estimating input bit error ratio
    1.
    发明授权
    Method and device for estimating input bit error ratio 有权
    用于估计输入误码率的方法和装置

    公开(公告)号：US09081677B2

    公开(公告)日：2015-07-14

    申请号：US13982403

    申请日：2012-02-20

    申请人： Yoshikuni Miyata ,  Kenya Sugihara ,  Kiyoshi Onohara ,  Kazuo Kubo ,  Hideo Yoshida ,  Takashi Mizuochi

    发明人： Yoshikuni Miyata ,  Kenya Sugihara ,  Kiyoshi Onohara ,  Kazuo Kubo ,  Hideo Yoshida ,  Takashi Mizuochi

    IPC分类号： G06F11/07 ,  H04L1/20

    CPC分类号： G06F11/076 ,  H04L1/203

    摘要： An input bit error ratio estimating method executed by a communication control unit includes a computing, a condition determining, a first input BER estimating, a second input BER estimating, a third input BER estimating, and an input BER estimation result outputting. In the condition determining, the communication control unit determines which of a plurality of conditions set in advance to be narrowed down to one has been established, based on a post-internal decoding residual error detection ratio. Based on the condition that is determined in the condition determining as one that has been established, the communication control unit selects one out of a plurality of processing procedures for estimating the input BER, namely, selects one of the first input BER estimating to the third input BER estimating and executes the selected processing.

    摘要翻译： 由通信控制单元执行的输入误码率估计方法包括计算，条件确定，第一输入BER估计，第二输入BER估计，第三输入BER估计和输入BER估计结果输出。 在所述条件判定中，所述通信控制部基于所述内部解码剩余错误检测率，确定预先设定为被缩小为一个的条件中的哪一个已被建立。 基于在确定为已经建立的条件中确定的条件，通信控制单元从用于估计输入BER的多个处理过程中选择一个，即，选择第三输入BER中的一个， 输入BER估计并执行所选择的处理。

    METHOD AND DEVICE FOR ESTIMATING INPUT BIT ERROR RATIO
    6.
    发明申请
    METHOD AND DEVICE FOR ESTIMATING INPUT BIT ERROR RATIO 有权
    用于估计输入位错误比率的方法和装置

    公开(公告)号：US20130311840A1

    公开(公告)日：2013-11-21

    申请号：US13982403

    申请日：2012-02-20

    申请人： Yoshikuni Miyata ,  Kenya Sugihara ,  Kiyoshi Onohara ,  Kazuo Kubo ,  Hideo Yoshida ,  Takashi Mizuochi

    发明人： Yoshikuni Miyata ,  Kenya Sugihara ,  Kiyoshi Onohara ,  Kazuo Kubo ,  Hideo Yoshida ,  Takashi Mizuochi

    IPC分类号： G06F11/07

    CPC分类号： G06F11/076 ,  H04L1/203

    摘要： An input bit error ratio estimating method executed by a communication control unit includes a computing, a condition determining, a first input BER estimating, a second input BER estimating, a third input BER estimating, and an input BER estimation result outputting. In the condition determining, the communication control unit determines which of a plurality of conditions set in advance to be narrowed down to one has been established, based on a post-internal decoding residual error detection ratio. Based on the condition that is determined in the condition determining as one that has been established, the communication control unit selects one out of a plurality of processing procedures for estimating the input BER, namely, selects one of the first input BER estimating to the third input BER estimating and executes the selected processing.

    摘要翻译： 由通信控制单元执行的输入误码率估计方法包括计算，条件确定，第一输入BER估计，第二输入BER估计，第三输入BER估计和输入BER估计结果输出。 在所述条件判定中，所述通信控制部基于所述内部解码剩余错误检测率，确定预先设定为被缩小为一个的条件中的哪一个已被建立。 基于在确定为已经建立的条件中确定的条件，通信控制单元从用于估计输入BER的多个处理过程中选择一个，即，选择第三输入BER中的一个， 输入BER估计并执行所选择的处理。

    Multiple coding method and apparatus, multiple decoding method and apparatus, and information transmission system
    9.
    发明授权
    Multiple coding method and apparatus, multiple decoding method and apparatus, and information transmission system 有权
    多重编码方法和装置，多重解码方法和装置以及信息传输系统

    公开(公告)号：US06658605B1

    公开(公告)日：2003-12-02

    申请号：US09703638

    申请日：2000-11-02

    申请人： Hideo Yoshida ,  Takahiko Nakamura ,  Hachiro Fujita ,  Yoshikuni Miyata ,  Kazuo Kubo

    发明人： Hideo Yoshida ,  Takahiko Nakamura ,  Hachiro Fujita ,  Yoshikuni Miyata ,  Kazuo Kubo

    IPC分类号： G11C2900

    CPC分类号： H03M7/30 ,  H03M13/15 ,  H03M13/1515 ,  H03M13/2707 ,  H03M13/2721 ,  H03M13/29 ,  H03M13/6561

    摘要： A multiple coding apparatus comprises a first encoder for encoding a plurality of input sequences in parallel so as to generate a plurality of output coded sequences in parallel while adding an error-correcting bit sequence to each of the plurality of input sequences. An interleaving circuit interleaves the plurality of output coded sequences applied thereto in parallel from the first encoder without having to use any memory. The interleaving circuit permutes the plurality of input sequences on a bit-by-bit or symbol-by-symbol basis so as to generate a plurality of interleaved coded sequences in parallel. A second encoder then encodes the plurality of interleaved coded sequences applied thereto in parallel from the interleaving circuit so as to generate a plurality of output coded sequences in parallel while adding an error-correcting bit sequence to each of the plurality of interleaved coded sequences.

    摘要翻译： 多重编码装置包括：并行地编码多个输入序列的第一编码器，以便并行地产生多个输出编码序列，同时向多个输入序列中的每个输入序列添加纠错位序列。 交织电路将从第一编码器并行地施加到其上的多个输出编码序列进行交织，而不必使用任何存储器。 交织电路逐位或逐符号地排列多个输入序列，以便并行地生成多个交错编码序列。 然后，第二编码器对从交织电路并行施加到其上的多个交错编码序列进行编码，以便并行地产生多个输出编码序列，同时向多个交错编码序列中的每一个添加纠错位序列。

    ERROR CORRECTION CODING DEVICE, ERROR CORRECTION DECODING DEVICE AND METHOD THEREFOR
    10.
    发明申请
    ERROR CORRECTION CODING DEVICE, ERROR CORRECTION DECODING DEVICE AND METHOD THEREFOR 有权
    错误校正编码装置，错误校正解码装置及其方法

    公开(公告)号：US20130311847A1

    公开(公告)日：2013-11-21

    申请号：US13982919

    申请日：2012-05-30

    申请人： Yoshikuni Miyata ,  Wataru Matsumoto ,  Hideo Yoshida ,  Kazuo Kubo

    发明人： Yoshikuni Miyata ,  Wataru Matsumoto ,  Hideo Yoshida ,  Kazuo Kubo

    IPC分类号： H03M13/29

    CPC分类号： H03M13/29 ,  H03M13/1102 ,  H03M13/1145 ,  H03M13/152 ,  H03M13/2909 ,  H03M13/356

    摘要： Provided is an error correction encoder that performs coding on both a transmission area and a redundancy area of the transmission frame by using a product code, and when excess or deficiency is arisen with respect to allocation of an information sequence area and/or a parity sequence area in a product code frame generated by the coding using the product code, non-uniformly allocate the information sequence area to the parity sequence area, and/or non-uniformly allocate the parity sequence area to the information sequence area, where each of the non-uniform allocations is performed in accordance with the arisen excess or deficiency.

    摘要翻译： 提供了一种纠错编码器，其通过使用产品代码对发送帧的发送区域和冗余区域两者进行编码，并且当相对于信息序列区域和/或奇偶校验序列的分配产生过多或不足时 通过使用产品代码的编码生成的商品代码帧中的区域，将信息序列区域均匀地分配给奇偶校验序列区域，和/或非均匀地将奇偶校验序列区域分配给信息序列区域，其中， 根据发生的过量或不足，进行非均匀分配。