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1.发明授权Multiple coding method and apparatus, multiple decoding method and apparatus, and information transmission system 有权多重编码方法和装置，多重解码方法和装置以及信息传输系统公开(公告)号：US06658605B1
公开(公告)日：2003-12-02
申请号：US09703638
申请日：2000-11-02
IPC分类号： G11C2900
CPC分类号： H03M7/30 , H03M13/15 , H03M13/1515 , H03M13/2707 , H03M13/2721 , H03M13/29 , H03M13/6561
摘要： A multiple coding apparatus comprises a first encoder for encoding a plurality of input sequences in parallel so as to generate a plurality of output coded sequences in parallel while adding an error-correcting bit sequence to each of the plurality of input sequences. An interleaving circuit interleaves the plurality of output coded sequences applied thereto in parallel from the first encoder without having to use any memory. The interleaving circuit permutes the plurality of input sequences on a bit-by-bit or symbol-by-symbol basis so as to generate a plurality of interleaved coded sequences in parallel. A second encoder then encodes the plurality of interleaved coded sequences applied thereto in parallel from the interleaving circuit so as to generate a plurality of output coded sequences in parallel while adding an error-correcting bit sequence to each of the plurality of interleaved coded sequences.
摘要翻译： 多重编码装置包括：并行地编码多个输入序列的第一编码器，以便并行地产生多个输出编码序列，同时向多个输入序列中的每个输入序列添加纠错位序列。 交织电路将从第一编码器并行地施加到其上的多个输出编码序列进行交织，而不必使用任何存储器。 交织电路逐位或逐符号地排列多个输入序列，以便并行地生成多个交错编码序列。 然后，第二编码器对从交织电路并行施加到其上的多个交错编码序列进行编码，以便并行地产生多个输出编码序列，同时向多个交错编码序列中的每一个添加纠错位序列。
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公开(公告)号：US07069496B2
公开(公告)日：2006-06-27
申请号：US10284391
申请日：2002-10-31
IPC分类号： H03M13/00
CPC分类号： H04L1/0066 , H03M13/136 , H03M13/151 , H03M13/152 , H03M13/19 , H03M13/2909 , H03M13/2927 , H03M13/2948 , H03M13/3738 , H03M13/45 , H03M13/451 , H03M13/6306 , H03M13/6561 , H04L1/005 , H04L1/1835 , H04L1/1874
摘要： A decoding apparatus generates error position sets of data sequence by generating a codeword from positions of soft input values output from a low reliability position detecting circuit and from syndromes computed by a syndrome calculation circuit. The recording apparatus further includes a codeword candidate generating circuit that computes correlation mismatch amounts by adding soft input values at the error positions contained in the error position sets, and updates the correction information according to the error position sets and correlation mismatch amounts. The decoding apparatus can calculate the soft output values accurately by utilizing the generated codeword candidates efficiently, and reduce the circuit scale by decreasing the amount of computation.
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3.发明授权Error correction encoding method and apparatus, and error correction decoding method and apparatus 失效纠错编码方法和装置，以及纠错解码方法和装置公开(公告)号：US06912684B2
公开(公告)日：2005-06-28
申请号：US10097347
申请日：2002-03-15
CPC分类号： H03M13/2987 , H03M13/2957 , H03M13/2963 , H03M13/2972 , H03M13/2981 , H03M13/3776
摘要： An error correction encoding method and apparatus, and an error correction decoding method and apparatus are provided without requiring transmission of tail bits. A turbo encoding step (ST41-ST45) and a transmission termination processing step (ST46→ST44-ST47) are included. In the turbo encoding step, a transmission information bit sequence is divided into a plurality of frames. Registers in each recursive systematic convolutional encoder are initialized before turbo encoding of a first frame. After turbo encoding of the first frame is carried out, a second frame and following frames are continuously subjected to turbo encoding without initializing the registers in each recursive systematic convolutional encoder before the turbo encoding of the second frame and following frames. In a transmission termination processing step, tail bits for initializing the registers in each recursive systematic convolutional encoder are calculated only after a final frame has been subjected to turbo encoding.
摘要翻译： 提供纠错编码方法和装置以及纠错解码方法和装置，而不需要传输尾比特。 包括turbo编码步骤（ST 41 -ST 45）和发送终止处理步骤（ST 46-> ST 44 -ST 47）。 在turbo编码步骤中，发送信息比特序列被分成多个帧。 每个递归系统卷积编码器中的寄存器在第一帧的turbo编码之前被初始化。 在执行第一帧的turbo编码之后，在第二帧和后续帧的turbo编码之前，第二帧和后续帧被连续地进行turbo编码，而不在每个递归系统卷积编码器中初始化寄存器。 在传输终止处理步骤中，仅在最后一帧已进行turbo编码之后才计算用于初始化每个递归系统卷积编码器中的寄存器的尾比特。
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公开(公告)号：US20080246639A1
公开(公告)日：2008-10-09
申请号：US11791996
申请日：2005-12-01
IPC分类号： H03M7/00
CPC分类号： H03M13/1188 , H03M13/1117 , H03M13/112 , H03M13/1137 , H03M13/114 , H03M13/118 , H03M13/1185 , H03M13/3911 , H03M13/6583 , H04L1/005 , H04L1/0057
摘要： A decoding apparatus includes a row processing unit 5 and a column processing unit 6 for performing a calculation and an update of probability information with row processing and column processing according to a Min-Sum algorithm on a received signal which is low-density parity-check coded in batches of 1 bit or a predetermined number of bits, a decoded result judgment unit 8 for determining a decoded result from a hard decision of a posterior value, for performing a parity check on the decoded result, and for judging whether or not the decoded result is correct, and a control unit for controlling iteration of decoding processing by the row processing unit 5 and column processing unit 6 on the basis of the judgment result of the decoded result judgment unit 8.
摘要翻译： 解码装置包括：行处理单元5和列处理单元6，用于对接收到的信号进行低密度奇偶校验，根据最小和算法对行处理和列处理进行概率信息的计算和更新 以1比特或预定比特数的批次编码的解码结果判断单元8，用于从后验值的硬判定中确定解码结果，用于对解码结果进行奇偶校验，并判断是否 解码结果是正确的，以及控制单元，用于根据解码结果判断单元8的判断结果控制行处理单元5和列处理单元6的解码处理的迭代。
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公开(公告)号：US07992069B2
公开(公告)日：2011-08-02
申请号：US11883958
申请日：2006-02-03
申请人： Yoshikuni Miyata , Hideo Yoshida , Kazuo Kubo
发明人： Yoshikuni Miyata , Hideo Yoshida , Kazuo Kubo
IPC分类号： H03M13/00
CPC分类号： H03M13/2906 , H03M13/134 , H04L1/0041 , H04L1/0057 , H04L1/0064 , H04L1/0083
摘要： An error correction coding apparatus divides transmission information sequences in n subframes (n is an arbitrary natural number) into n1 subframes (n1 is a natural number
摘要翻译： 纠错编码装置将n个子帧（n为任意自然数）中的发送信息序列分割为n1个子帧（n1为自然数
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公开(公告)号：US08201047B2
公开(公告)日：2012-06-12
申请号：US11791996
申请日：2005-12-01
IPC分类号： H03M13/00
CPC分类号： H03M13/1188 , H03M13/1117 , H03M13/112 , H03M13/1137 , H03M13/114 , H03M13/118 , H03M13/1185 , H03M13/3911 , H03M13/6583 , H04L1/005 , H04L1/0057
摘要： A decoding apparatus includes a row processing unit 5 and a column processing unit 6 for performing a calculation and an update of probability information with row processing and column processing according to a Min-Sum algorithm on a received signal which is low-density parity-check coded in batches of 1 bit or a predetermined number of bits, a decoded result judgment unit 8 for determining a decoded result from a hard decision of a posterior value, for performing a parity check on the decoded result, and for judging whether or not the decoded result is correct, and a control unit for controlling iteration of decoding processing by the row processing unit 5 and column processing unit 6 on the basis of the judgment result of the decoded result judgment unit 8.
摘要翻译： 解码装置包括：行处理单元5和列处理单元6，用于对接收到的信号进行低密度奇偶校验，根据最小和算法对行处理和列处理进行概率信息的计算和更新 以1比特或预定比特数的批次编码的解码结果判断单元8，用于从后验值的硬判定中确定解码结果，用于对解码结果进行奇偶校验，并判断是否 解码结果是正确的，以及控制单元，用于根据解码结果判断单元8的判断结果控制行处理单元5和列处理单元6的解码处理的迭代。
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7.发明授权Test matrix generating method, encoding method, decoding method, communication apparatus, communication system, encoder and decoder 有权测试矩阵生成方法，编码方法，解码方法，通信装置，通信系统，编码器和解码器公开(公告)号：US08103935B2
公开(公告)日：2012-01-24
申请号：US12063507
申请日：2006-07-31
IPC分类号： G06F11/00
CPC分类号： H03M13/116 , H03M13/1117 , H03M13/1122 , H03M13/1137 , H03M13/6362 , H04L1/0057
摘要： A regular quasi-cyclic matrix is prepared, a conditional expression for assuring a predetermined minimum loop in a parity check matrix is derived, and a mask matrix for converting a specific cyclic permutation matrix into a zero-matrix based on the conditional expression and a predetermined weight distribution is generated. The specific cyclic permutation matrix is converted into the zero-matrix to generate an irregular masking quasi-cyclic matrix. An irregular parity check matrix in which the masking quasi-cyclic matrix and a matrix in which the cyclic permutation matrices are arranged in a staircase manner are arranged in a predetermined location.
摘要翻译： 准备规则准循环矩阵，导出用于确定奇偶校验矩阵中的预定最小循环的条件表达式，以及用于将特定循环置换矩阵转换成基于条件表达式的零矩阵的掩码矩阵， 产生重量分布。 特定的循环置换矩阵被转换为零矩阵以产生不规则的掩蔽准循环矩阵。 其中掩蔽准循环矩阵和其中循环置换矩阵以阶梯排列的矩阵布置在预定位置的不规则奇偶校验矩阵。
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8.发明申请TEST MATRIX GENERATING METHOD, ENCODING METHOD, DECODING METHOD, COMMUNICATION APPARATUS, COMMUNICATION SYSTEM, ENCODER AND DECODER 有权测试矩阵生成方法，编码方法，解码方法，通信设备，通信系统，编码器和解码器公开(公告)号：US20090265600A1
公开(公告)日：2009-10-22
申请号：US12063507
申请日：2006-07-31
CPC分类号： H03M13/116 , H03M13/1117 , H03M13/1122 , H03M13/1137 , H03M13/6362 , H04L1/0057
摘要： A regular quasi-cyclic matrix is prepared, a conditional expression for assuring a predetermined minimum loop in a parity check matrix is derived, and a mask matrix for converting a specific cyclic permutation matrix into a zero-matrix based on the conditional expression and a predetermined weight distribution is generated. The specific cyclic permutation matrix is converted into the zero-matrix to generate an irregular masking quasi-cyclic matrix. An irregular parity check matrix in which the masking quasi-cyclic matrix and a matrix in which the cyclic permutation matrices are arranged in a staircase manner are arranged in a predetermined location.
摘要翻译： 准备规则准循环矩阵，导出用于确定奇偶校验矩阵中的预定最小循环的条件表达式，以及用于将特定循环置换矩阵转换成基于条件表达式的零矩阵的掩码矩阵， 产生重量分布。 特定的循环置换矩阵被转换为零矩阵以产生不规则的掩蔽准循环矩阵。 其中掩蔽准循环矩阵和其中循环置换矩阵以阶梯排列的矩阵布置在预定位置的不规则奇偶校验矩阵。
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公开(公告)号：US09081677B2
公开(公告)日：2015-07-14
申请号：US13982403
申请日：2012-02-20
申请人： Yoshikuni Miyata , Kenya Sugihara , Kiyoshi Onohara , Kazuo Kubo , Hideo Yoshida , Takashi Mizuochi
发明人： Yoshikuni Miyata , Kenya Sugihara , Kiyoshi Onohara , Kazuo Kubo , Hideo Yoshida , Takashi Mizuochi
CPC分类号： G06F11/076 , H04L1/203
摘要： An input bit error ratio estimating method executed by a communication control unit includes a computing, a condition determining, a first input BER estimating, a second input BER estimating, a third input BER estimating, and an input BER estimation result outputting. In the condition determining, the communication control unit determines which of a plurality of conditions set in advance to be narrowed down to one has been established, based on a post-internal decoding residual error detection ratio. Based on the condition that is determined in the condition determining as one that has been established, the communication control unit selects one out of a plurality of processing procedures for estimating the input BER, namely, selects one of the first input BER estimating to the third input BER estimating and executes the selected processing.
摘要翻译： 由通信控制单元执行的输入误码率估计方法包括计算，条件确定，第一输入BER估计，第二输入BER估计，第三输入BER估计和输入BER估计结果输出。 在所述条件判定中，所述通信控制部基于所述内部解码剩余错误检测率，确定预先设定为被缩小为一个的条件中的哪一个已被建立。 基于在确定为已经建立的条件中确定的条件，通信控制单元从用于估计输入BER的多个处理过程中选择一个，即，选择第三输入BER中的一个， 输入BER估计并执行所选择的处理。
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10.发明授权Method and device for encoding of error correcting codes, and method and device for decoding of error correcting codes 有权用于纠错码编码的方法和装置，以及用于解码纠错码的方法和装置公开(公告)号：US08621316B2
公开(公告)日：2013-12-31
申请号：US12987368
申请日：2011-01-10
申请人： Yoshikuni Miyata , Hideo Yoshida , Kazuo Kubo , Takashi Mizuochi
发明人： Yoshikuni Miyata , Hideo Yoshida , Kazuo Kubo , Takashi Mizuochi
CPC分类号： H04L1/0071 , H03M13/1102 , H03M13/1515 , H03M13/152 , H03M13/23 , H03M13/271 , H03M13/29 , H03M13/2945 , H03M13/2957 , H03M13/2963 , H03M13/356 , H03M13/6561 , H03M13/6577 , H04L1/0065
摘要： An error correction encoding device includes an outer encoding circuit that performs encoding processing for an outer code and an inner encoding circuit that performs encoding processing for an inner code. The inner encoding circuit includes an inner-encoding input circuit that performs interleaving processing in which a parallel input sequence is divided into lanes and in which a barrel shift is performed for each inner frame in the lanes. Thus, allocation ratios between an information sequence area and a parity sequence area are made uniform.
摘要翻译： 纠错编码装置包括对外部码进行编码处理的外部编码电路和对内部码进行编码处理的内部编码电路。 内部编码电路包括内部编码输入电路，其执行交织处理，其中并行输入序列被划分为通道，并且其中对车道中的每个内部框架执行桶形移位。 因此，使信息序列区域和奇偶序列区域之间的分配比率一致。
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