公开(公告)号：US07323351B2

公开(公告)日：2008-01-29

申请号：US11183701

申请日：2005-07-18

申请人： Kazushige Hotta ,  Hiroyuki Yaegashi ,  Takuya Watanabe ,  Tamotsu Wada

发明人： Kazushige Hotta ,  Hiroyuki Yaegashi ,  Takuya Watanabe ,  Tamotsu Wada

IPC分类号： H01L21/84

CPC分类号： H01L27/1288 ,  H01L27/1214 ,  H01L27/3248 ,  H01L29/42384 ,  H01L29/4908 ,  H01L29/66757 ,  H01L29/78621 ,  H01L2029/7863 ,  H01L2227/323

摘要： A polysilicon film is formed in a predetermined region on a glass substrate, and then a gate insulating film and a gate electrode, whose width is narrower than the gate insulating film, are formed thereon. Then, an interlayer insulating film and an ITO film are formed on an overall surface. Then, n-type source/drain regions having an LDD structure are formed by implanting the n-type impurity into the polysilicon film. Then, an n-type TFT forming region and a pixel-electrode forming region are covered with a resist film, and then p-type source/drain regions are formed by implanting the p-type impurity into the polysilicon film in a p-type TFT forming region. Then, the resist film is left only in the pixel-electrode forming region and the resist film is removed from other regions. A pixel electrode is formed by etching the ITO film while using the remaining resist film as a mask.

摘要翻译： 在玻璃基板上的预定区域中形成多晶硅膜，然后在其上形成宽度比栅极绝缘膜窄的栅极绝缘膜和栅极电极。 然后，在整个表面上形成层间绝缘膜和ITO膜。 然后，通过将n型杂质注入多晶硅膜形成具有LDD结构的n型源/漏区。 然后，用抗蚀剂膜覆盖n型TFT形成区域和像素电极形成区域，然后通过以p型将p型杂质注入多晶硅膜形成p型源极/漏极区域 TFT形成区域。 然后，抗蚀剂膜仅留在像素电极形成区域中，并且抗蚀剂膜从其它区域去除。 通过在使用剩余的抗蚀剂膜作为掩模的同时蚀刻ITO膜来形成像素电极。

公开(公告)号：US20050269572A1

公开(公告)日：2005-12-08

申请号：US11183701

申请日：2005-07-18

申请人： Kazushige Hotta ,  Hiroyuki Yaegashi ,  Takuya Watanabe ,  Tamotsu Wada

发明人： Kazushige Hotta ,  Hiroyuki Yaegashi ,  Takuya Watanabe ,  Tamotsu Wada

IPC分类号： G02F1/1368 ,  C30B1/00 ,  G09F9/30 ,  H01L21/00 ,  H01L21/20 ,  H01L21/336 ,  H01L21/36 ,  H01L21/77 ,  H01L21/84 ,  H01L27/01 ,  H01L27/12 ,  H01L29/04 ,  H01L29/10 ,  H01L29/15 ,  H01L29/423 ,  H01L29/49 ,  H01L29/786 ,  H01L31/036 ,  H01L31/0376 ,  H01L31/20

CPC分类号： H01L27/1288 ,  H01L27/1214 ,  H01L27/3248 ,  H01L29/42384 ,  H01L29/4908 ,  H01L29/66757 ,  H01L29/78621 ,  H01L2029/7863 ,  H01L2227/323

摘要： A polysilicon film is formed in a predetermined region on a glass substrate, and then a gate insulating film and a gate electrode, whose width is narrower than the gate insulating film, are formed thereon. Then, an interlayer insulating film and an ITO film are formed on an overall surface. Then, n-type source/drain regions having an LDD structure are formed by implanting the n-type impurity into the polysilicon film. Then, an n-type TFT forming region and a pixel-electrode forming region are covered with a resist film, and then p-type source/drain regions are formed by implanting the p-type impurity into the polysilicon film in a p-type TFT forming region. Then, the resist film is left only in the pixel-electrode forming region and the resist film is removed from other regions. A pixel electrode is formed by etching the ITO film while using the remaining resist film as a mask.

公开(公告)号：US07279348B2

公开(公告)日：2007-10-09

申请号：US11183432

申请日：2005-07-18

申请人： Kazushige Hotta ,  Hiroyuki Yaegashi ,  Takuya Watanabe ,  Tamotsu Wada

发明人： Kazushige Hotta ,  Hiroyuki Yaegashi ,  Takuya Watanabe ,  Tamotsu Wada

IPC分类号： H01L21/84

CPC分类号： H01L27/1288 ,  H01L27/1214 ,  H01L27/3248 ,  H01L29/42384 ,  H01L29/4908 ,  H01L29/66757 ,  H01L29/78621 ,  H01L2029/7863 ,  H01L2227/323

摘要： A polysilicon film is formed in a predetermined region on a glass substrate, and then a gate insulating film and a gate electrode, whose width is narrower than the gate insulating film, are formed thereon. Then, an interlayer insulating film and an ITO film are formed on an overall surface. Then, n-type source/drain regions having an LDD structure are formed by implanting the n-type impurity into the polysilicon film. Then, an n-type TFT forming region and a pixel-electrode forming region are covered with a resist film, and then p-type source/drain regions are formed by implanting the p-type impurity into the polysilicon film in a p-type TFT forming region. Then, the resist film is left only in the pixel-electrode forming region and the resist film is removed from other regions. A pixel electrode is formed by etching the ITO film while using the remaining resist film as a mask.

摘要翻译： 在玻璃基板上的预定区域中形成多晶硅膜，然后在其上形成宽度比栅极绝缘膜窄的栅极绝缘膜和栅极电极。 然后，在整个表面上形成层间绝缘膜和ITO膜。 然后，通过将n型杂质注入多晶硅膜形成具有LDD结构的n型源/漏区。 然后，用抗蚀剂膜覆盖n型TFT形成区域和像素电极形成区域，然后通过以p型将p型杂质注入多晶硅膜形成p型源极/漏极区域 TFT形成区域。 然后，抗蚀剂膜仅留在像素电极形成区域中，并且抗蚀剂膜从其它区域去除。 通过在使用剩余的抗蚀剂膜作为掩模的同时蚀刻ITO膜来形成像素电极。

公开(公告)号：US07161181B2

公开(公告)日：2007-01-09

申请号：US11183383

申请日：2005-07-18

申请人： Kazushige Hotta ,  Hiroyuki Yaegashi ,  Takuya Watanabe ,  Tamotsu Wada

发明人： Kazushige Hotta ,  Hiroyuki Yaegashi ,  Takuya Watanabe ,  Tamotsu Wada

IPC分类号： H01L21/00

CPC分类号： H01L27/1288 ,  H01L27/1214 ,  H01L27/3248 ,  H01L29/42384 ,  H01L29/4908 ,  H01L29/66757 ,  H01L29/78621 ,  H01L2029/7863 ,  H01L2227/323

摘要： A polysilicon film is formed in a predetermined region on a glass substrate, and then a gate insulating film and a gate electrode, whose width is narrower than the gate insulating film, are formed thereon. Then, an interlayer insulating film and an ITO film are formed on an overall surface. Then, n-type source/drain regions having an LDD structure are formed by implanting the n-type impurity into the polysilicon film. Then, an n-type TFT forming region and a pixel-electrode forming region are covered with a resist film, and then p-type source/drain regions are formed by implanting the p-type impurity into the polysilicon film in a p-type TFT forming region. Then, the resist film is left only in the pixel-electrode forming region and the resist film is removed from other regions. A pixel electrode is formed by etching the ITO film while using the remaining resist film as a mask.

公开(公告)号：US20050255621A1

公开(公告)日：2005-11-17

申请号：US11183383

申请日：2005-07-18

申请人： Kazushige Hotta ,  Hiroyuki Yaegashi ,  Takuya Watanabe ,  Tamotsu Wada

发明人： Kazushige Hotta ,  Hiroyuki Yaegashi ,  Takuya Watanabe ,  Tamotsu Wada

IPC分类号： G02F1/1368 ,  C30B1/00 ,  G09F9/30 ,  H01L21/00 ,  H01L21/20 ,  H01L21/336 ,  H01L21/36 ,  H01L21/77 ,  H01L21/84 ,  H01L27/01 ,  H01L27/12 ,  H01L29/04 ,  H01L29/10 ,  H01L29/15 ,  H01L29/423 ,  H01L29/49 ,  H01L29/786 ,  H01L31/036 ,  H01L31/0376 ,  H01L31/20

CPC分类号： H01L27/1288 ,  H01L27/1214 ,  H01L27/3248 ,  H01L29/42384 ,  H01L29/4908 ,  H01L29/66757 ,  H01L29/78621 ,  H01L2029/7863 ,  H01L2227/323

摘要： A polysilicon film is formed in a predetermined region on a glass substrate, and then a gate insulating film and a gate electrode, whose width is narrower than the gate insulating film, are formed thereon. Then, an interlayer insulating film and an ITO film are formed on an overall surface. Then, n-type source/drain regions having an LDD structure are formed by implanting the n-type impurity into the polysilicon film. Then, an n-type TFT forming region and a pixel-electrode forming region are covered with a resist film, and then p-type source/drain regions are formed by implanting the p-type impurity into the polysilicon film in a p-type TFT forming region. Then, the resist film is left only in the pixel-electrode forming region and the resist film is removed from other regions. A pixel electrode is formed by etching the ITO film while using the remaining resist film as a mask.

公开(公告)号：US20050250264A1

公开(公告)日：2005-11-10

申请号：US11183432

申请日：2005-07-18

申请人： Kazushige Hotta ,  Hiroyuki Yaegashi ,  Takuya Watanabe ,  Tamotsu Wada

发明人： Kazushige Hotta ,  Hiroyuki Yaegashi ,  Takuya Watanabe ,  Tamotsu Wada

IPC分类号： G02F1/1368 ,  C30B1/00 ,  G09F9/30 ,  H01L21/00 ,  H01L21/20 ,  H01L21/336 ,  H01L21/36 ,  H01L21/77 ,  H01L21/84 ,  H01L27/01 ,  H01L27/12 ,  H01L29/04 ,  H01L29/10 ,  H01L29/15 ,  H01L29/423 ,  H01L29/49 ,  H01L29/786 ,  H01L31/036 ,  H01L31/0376 ,  H01L31/20

CPC分类号： H01L27/1288 ,  H01L27/1214 ,  H01L27/3248 ,  H01L29/42384 ,  H01L29/4908 ,  H01L29/66757 ,  H01L29/78621 ,  H01L2029/7863 ,  H01L2227/323

摘要： A polysilicon film is formed in a predetermined region on a glass substrate, and then a gate insulating film and a gate electrode, whose width is narrower than the gate insulating film, are formed thereon. Then, an interlayer insulating film and an ITO film are formed on an overall surface. Then, n-type source/drain regions having an LDD structure are formed by implanting the n-type impurity into the polysilicon film. Then, an n-type TFT forming region and a pixel-electrode forming region are covered with a resist film, and then p-type source/drain regions are formed by implanting the p-type impurity into the polysilicon film in a p-type TFT forming region. Then, the resist film is left only in the pixel-electrode forming region and the resist film is removed from other regions. A pixel electrode is formed by etching the ITO film while using the remaining resist film as a mask.

摘要翻译： 在玻璃基板上的预定区域中形成多晶硅膜，然后在其上形成宽度比栅极绝缘膜窄的栅极绝缘膜和栅极电极。 然后，在整个表面上形成层间绝缘膜和ITO膜。 然后，通过将n型杂质注入多晶硅膜形成具有LDD结构的n型源/漏区。 然后，用抗蚀剂膜覆盖n型TFT形成区域和像素电极形成区域，然后通过以p型将p型杂质注入多晶硅膜形成p型源极/漏极区域 TFT形成区域。 然后，抗蚀剂膜仅留在像素电极形成区域中，并且抗蚀剂膜从其它区域去除。 通过在使用剩余的抗蚀剂膜作为掩模的同时蚀刻ITO膜来形成像素电极。

公开(公告)号：US06939750B2

公开(公告)日：2005-09-06

申请号：US10839643

申请日：2004-05-05

申请人： Kazushige Hotta ,  Hiroyuki Yaegashi ,  Takuya Watanabe ,  Tamotsu Wada

发明人： Kazushige Hotta ,  Hiroyuki Yaegashi ,  Takuya Watanabe ,  Tamotsu Wada

IPC分类号： G02F1/1368 ,  C30B1/00 ,  G09F9/30 ,  H01L21/00 ,  H01L21/20 ,  H01L21/336 ,  H01L21/36 ,  H01L21/77 ,  H01L21/84 ,  H01L27/01 ,  H01L27/12 ,  H01L29/04 ,  H01L29/10 ,  H01L29/15 ,  H01L29/423 ,  H01L29/49 ,  H01L29/786 ,  H01L31/036 ,  H01L31/0376 ,  H01L31/20

CPC分类号： H01L27/1288 ,  H01L27/1214 ,  H01L27/3248 ,  H01L29/42384 ,  H01L29/4908 ,  H01L29/66757 ,  H01L29/78621 ,  H01L2029/7863 ,  H01L2227/323

摘要： A polysilicon film is formed in a predetermined region on a glass substrate, and then a gate insulating film and a gate electrode, whose width is narrower than the gate insulating film, are formed thereon. Then, an interlayer insulating film and an ITO film are formed on an overall surface. Then, n-type source/drain regions having an LDD structure are formed by implanting the n-type impurity into the polysilicon film. Then, an n-type TFT forming region and a pixel-electrode forming region are covered with a resist film, and then p-type source/drain regions are formed by implanting the p-type impurity into the polysilicon film in a p-type TFT forming region. Then, the resist film is left only in the pixel-electrode forming region and the resist film is removed from other regions. A pixel electrode is formed by etching the ITO film while using the remaining resist film as a mask.

公开(公告)号：US6130456A

公开(公告)日：2000-10-10

申请号：US956772

申请日：1997-10-22

申请人： Ken-ichi Oki ,  Ken-ichi Yanai ,  Tamotsu Wada ,  Koji Ohgata ,  Yutaka Takizawa ,  Masahiro Okabe ,  Tsutomu Tanaka

发明人： Ken-ichi Oki ,  Ken-ichi Yanai ,  Tamotsu Wada ,  Koji Ohgata ,  Yutaka Takizawa ,  Masahiro Okabe ,  Tsutomu Tanaka

IPC分类号： G02F1/1362 ,  G02F1/1368 ,  H01L21/77 ,  H01L21/84

CPC分类号： H01L27/124 ,  G02F1/136286 ,  G02F1/1368 ,  G02F2001/136295 ,  H01L29/41733

摘要： A thin film transistor matrix device comprises an insulating substrate, a plurality of picture element electrodes arranged in a matrix on the insulating substrate, source electrodes connected to the respective picture element electrodes, drain electrodes opposed to the respective source electrodes, operational semiconductor layers sandwiched by the source electrodes and the drain electrodes, and gate electrodes formed on the operational semiconductor layers through gate insulating films, each gate electrode being narrowed with respect to the associated gate insulating film so that side walls of the gate electrode forms a step with respect to side walls of the associated gate insulating film which is a substrate of the gate electrode. The gate electrode is made narrower with respect to the gate insulating film to form a step between the side walls of the gate electrode with respect to those of the gate insulating film, whereby leak currents from the source electrode or the drain electrode to the gate electrode along the mesa side surfaces of the TFT can be simply suppressed. Accordingly a TFT matrix device having little wasteful current consumption can be realized.

摘要翻译： 薄膜晶体管矩阵器件包括绝缘衬底，在绝缘衬底上以矩阵形式布置的多个像素电极，连接到各个像素电极的源电极，与各个源电极相对的漏极电极，被 源电极和漏极以及通过栅极绝缘膜形成在工作半导体层上的栅电极，每个栅电极相对于相关的栅极绝缘膜变窄，使得栅电极的侧壁相对于侧面形成一个台阶 作为栅电极的基板的相关栅极绝缘膜的壁。 使栅电极相对于栅极绝缘膜变窄，在栅电极的侧壁之间相对于栅极绝缘膜的侧壁形成台阶，由此从源电极或漏电极到栅电极的漏电流 沿着TFT的台面侧表面可以简单地抑制。 因此，可以实现具有少量浪费电流消耗的TFT矩阵装置。

公开(公告)号：US5994173A

公开(公告)日：1999-11-30

申请号：US941224

申请日：1997-09-26

申请人： Ken-ichi Oki ,  Ken-ichi Yanai ,  Tamotsu Wada ,  Koji Ohgata ,  Yutaka Takizawa ,  Masahiro Okabe ,  Tsutomu Tanaka

发明人： Ken-ichi Oki ,  Ken-ichi Yanai ,  Tamotsu Wada ,  Koji Ohgata ,  Yutaka Takizawa ,  Masahiro Okabe ,  Tsutomu Tanaka

IPC分类号： G02F1/1362 ,  G02F1/1368 ,  H01L21/77 ,  H01L21/84 ,  H01L31/0392 ,  H01L21/306 ,  H01L29/78

CPC分类号： H01L27/124 ,  G02F1/136286 ,  G02F1/1368 ,  G02F2001/136295 ,  H01L29/41733

摘要： A thin film transistor matrix device comprises an insulating substrate, a plurality of picture element electrodes arranged in a matrix on the insulating substrate, source electrodes connected to the respective picture element electrodes, drain electrodes opposed to the respective source electrodes, operational semiconductor layers sandwiched by the source electrodes and the drain electrodes, and gate electrodes formed on the operational semiconductor layers through gate insulating films, each gate electrode being narrowed with respect to the associated gate insulating film so that side walls of the gate electrode forms a step with respect to side walls of the associated gate insulating film which is a substrate of the gate electrode. The gate electrode is made narrower with respect to the gate insulating film to form a step between the side walls of the gate electrode with respect to those of the gate insulating film, whereby leak currents from the source electrode or the drain electrode to the gate electrode along the mesa side surfaces of the TFT can be simply suppressed. Accordingly a TFT matrix device having little wasteful current consumption can be realized.

摘要翻译： 薄膜晶体管矩阵器件包括绝缘衬底，在绝缘衬底上以矩阵形式布置的多个像素电极，连接到各个像素电极的源电极，与各个源电极相对的漏极电极，被 源电极和漏极以及通过栅极绝缘膜形成在工作半导体层上的栅电极，每个栅电极相对于相关的栅极绝缘膜变窄，使得栅电极的侧壁相对于侧面形成一个台阶 作为栅电极的基板的相关栅极绝缘膜的壁。 使栅电极相对于栅极绝缘膜变窄，在栅电极的侧壁之间相对于栅极绝缘膜的侧壁形成台阶，由此从源电极或漏电极到栅电极的漏电流 沿着TFT的台面侧表面可以简单地抑制。 因此，可以实现具有少量浪费电流消耗的TFT矩阵装置。

公开(公告)号：US6156662A

公开(公告)日：2000-12-05

申请号：US281128

申请日：1999-03-29

申请人： Tatsuya Ohori ,  Tamotsu Wada ,  Kohji Ohgata ,  Tatsuya Kakehi ,  Ken-ichi Yanai

发明人： Tatsuya Ohori ,  Tamotsu Wada ,  Kohji Ohgata ,  Tatsuya Kakehi ,  Ken-ichi Yanai

IPC分类号： G02F1/136 ,  G02F1/1343 ,  G02F1/1362 ,  G02F1/1368 ,  H01L21/336 ,  H01L29/786 ,  H01L21/311

CPC分类号： G02F1/1362

摘要： A method of fabricating a liquid crystal display device includes the step of removing a porous anodic oxide film selectively with respect to a barrier-type anodic oxide film covering a gate electrode pattern of a thin-film transistor, wherein the step of removing the porous anodic oxide film is conducted after the step of disconnecting a bridging conductor pattern used for supplying electric current at the time of anodic oxidation process of the gate electrode.

摘要翻译： 一种制造液晶显示装置的方法包括相对于覆盖薄膜晶体管的栅电极图案的阻挡型阳极氧化膜选择性地去除多孔阳极氧化膜的步骤，其中除去多孔阳极 在栅电极的阳极氧化处理之后断开用于提供电流的桥接导体图案的步骤之后进行氧化膜。