公开(公告)号：US20090224794A1

公开(公告)日：2009-09-10

申请号：US12279767

申请日：2006-08-03

申请人： Kazuyuki Hyobu

发明人： Kazuyuki Hyobu

IPC分类号： G01R31/26 ,  H01L23/00

CPC分类号： G01R31/3008 ,  G01R31/31713 ,  G01R31/31717 ,  H01L2224/05554 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/49113 ,  H01L2224/49175 ,  H01L2924/13091 ,  H01L2924/3011 ,  H01L2924/00014 ,  H01L2924/00

摘要： An internal connection output pad (14A) connected to a CMOS output circuit (15A, 16A) on a first chip (11A) is electrically connected via a chip-to-chip bonding wire (17) to an internal connection input pad (14B) connected to a CMOS input circuit (15B, 16B) on a second chip (11B). In order to inspect the presence or absence of leakage resistance (40), a test circuit (30) controls a high-impedance output state, a high-level output state and a low-level output state of the internal connection output pad (14A) via the CMOS output circuit (15A, 16A). If a difference between a value obtained by measuring a current flowing through a power supply to a ground in the high-impedance output state and a value obtained by measuring such a current in the high-level output state is calculated, a transistor leakage current is canceled, so that a correct minute leakage current can be detected.

摘要翻译： 连接到第一芯片（11A）上的CMOS输出电路（15A，16A）的内部连接输出焊盘（14A）通过芯片 - 芯片接合线（17）电连接到内部连接输入焊盘（14B） 连接到第二芯片（11B）上的CMOS输入电路（15B，16B）。 为了检查是否存在泄漏电阻（40），测试电路（30）控制内部连接输出焊盘（14A）的高阻抗输出状态，高电平输出状态和低电平输出状态 ）经由CMOS输出电路（15A，16A）。 如果计算通过测量在高阻抗输出状态下流过电源到地的电流而获得的值与通过测量高电平输出状态下的电流而获得的值之间的差，则晶体管漏电流为 取消，从而可以检测到正确的微小泄漏电流。

公开(公告)号：US07843206B2

公开(公告)日：2010-11-30

申请号：US12279767

申请日：2006-08-03

申请人： Kazuyuki Hyobu

发明人： Kazuyuki Hyobu

IPC分类号： G01R31/02 ,  G01R31/26

CPC分类号： G01R31/3008 ,  G01R31/31713 ,  G01R31/31717 ,  H01L2224/05554 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/49113 ,  H01L2224/49175 ,  H01L2924/13091 ,  H01L2924/3011 ,  H01L2924/00014 ,  H01L2924/00

摘要： An internal connection output pad (14A) connected to a CMOS output circuit (15A, 16A) on a first chip (11A) is electrically connected via a chip-to-chip bonding wire (17) to an internal connection input pad (14B) connected to a CMOS input circuit (15B, 16B) on a second chip (11B). In order to inspect the presence or absence of leakage resistance (40), a test circuit (30) controls a high-impedance output state, a high-level output state and a low-level output state of the internal connection output pad (14A) via the CMOS output circuit (15A, 16A). If a difference between a value obtained by measuring a current flowing through a power supply to a ground in the high-impedance output state and a value obtained by measuring such a current in the high-level output state is calculated, a transistor leakage current is canceled, so that a correct minute leakage current can be detected.

摘要翻译： 连接到第一芯片（11A）上的CMOS输出电路（15A，16A）的内部连接输出焊盘（14A）通过芯片 - 芯片接合线（17）电连接到内部连接输入焊盘（14B） 连接到第二芯片（11B）上的CMOS输入电路（15B，16B）。 为了检查是否存在泄漏电阻（40），测试电路（30）控制内部连接输出焊盘（14A）的高阻抗输出状态，高电平输出状态和低电平输出状态 ）经由CMOS输出电路（15A，16A）。 如果计算通过测量在高阻抗输出状态下流过电源到地的电流而获得的值与通过测量高电平输出状态下的电流而获得的值之间的差，则晶体管漏电流为 取消，从而可以检测到正确的微小泄漏电流。

公开(公告)号：US06300891B1

公开(公告)日：2001-10-09

申请号：US09266601

申请日：1999-03-11

申请人： Yasunori Tani ,  Yoshinori Miyada ,  Kazuyuki Hyobu

发明人： Yasunori Tani ,  Yoshinori Miyada ,  Kazuyuki Hyobu

IPC分类号： H03M166

CPC分类号： H03M1/0665 ,  H03M1/66

摘要： To provide a D/A conversion apparatus that can minimize the increase in the amount of circuitry if the number of output levels is increased, a digital input value, input for each sampling clock, is first converted by a digital filter and a noise shaper into a word length limited digital signal with a high sampling frequency. The output of the noise shaper is mapped by a decoder to n m-valued signals a “1” at a time in a cyclic fashion progressing from one signal to the next so that the sum of the n m-valued signals becomes equal to the digital input value; thereafter, the n m-valued signals are converted by n m-valued D/A converters into corresponding analog signals which are then summed together by an analog adder to produce an analog output signal. The term “cyclic” means not only that one digital input value is mapped to the n m-valued signals a “1” at a time in a cyclic fashion progressing from one signal to the next, but also that the mapping of the present digital input value to the n m-valued signals is performed starting with the m-valued signal that immediately follows the m-valued signal to which the preceding digital input value was last mapped.

摘要翻译： 为了提供D / A转换装置，如果输出电平的数量增加，可以最小化电路量的增加，则每个采样时钟的输入的数字输入值首先由数字滤波器和噪声整形器转换成 具有高采样频率的字长限制数字信号。 噪声整形器的输出由解码器以从一个信号到下一个信号的循环方式一次映射到n个m值信号a“1”，使得n个m值信号的和变为等于 数字输入值; 此后，n个m值的信号由n个m值D / A转换器转换成相应的模拟信号，然后由模拟加法器将它们相加在一起以产生模拟输出信号。 术语“循环”不仅意味着一个数字输入值以一个从一个信号到下一个信号的循环方式一次被映射到n个m值信号a“1”，而且表示当前数字 从n个m值信号的输入值开始，以与上一个数字输入值最后映射到的m值信号紧邻的m值信号开始。