Semiconductor device
    2.
    发明授权
    Semiconductor device 有权
    半导体器件

    公开(公告)号:US08431967B2

    公开(公告)日:2013-04-30

    申请号:US13020566

    申请日:2011-02-03

    IPC分类号: H01L27/118

    CPC分类号: H01L27/0207

    摘要: A layout of a semiconductor device is capable of reliably reducing a variation in gate length due to the optical proximity effect, and enables flexible layout design to be implemented. Gate patterns (G1, G2, G3) of a cell (C1) are arranged at the same pitch, and terminal ends (e1, e2, e3) of the gate patterns are located at the same position in the Y direction, and have the same width in the X direction. A gate pattern (G4) of a cell (C2) has protruding portions (4b) protruding toward the cell (C1) in the Y direction, and the protruding portions (4b) form opposing terminal ends (eo1, eo2, eo3). The opposing terminal ends (eo1, eo2, eo3) are arranged at the same pitch as the gate patterns (G1, G2, G3), are located at the same position in the Y direction, and have the same width in the X direction.

    摘要翻译: 半导体器件的布局能够可靠地降低由于光学邻近效应引起的栅极长度的变化,并且能够实现灵活的布局设计。 单元(C1)的栅极图案(G1,G2,G3)以相同的间距排列,并且栅极图案的末端(e1,e2,e3)位于与Y方向相同的位置, 相同宽度的X方向。 电池(C2)的栅极图案(G4)具有在Y方向朝向电池单元(C1)突出的突出部分(4b),并且突出部分(4b)形成相对的末端(eo1,eo2,eo3)。 相对的末端(eo1,eo2,eo3)以与栅极图案(G1,G2,G3)相同的间距配置在与Y方向相同的位置,并且在X方向上具有相同的宽度。

    SEMICONDUCTOR INTEGRATED CIRCUIT
    3.
    发明申请
    SEMICONDUCTOR INTEGRATED CIRCUIT 有权
    半导体集成电路

    公开(公告)号:US20080224176A1

    公开(公告)日:2008-09-18

    申请号:US12048837

    申请日:2008-03-14

    IPC分类号: H01L27/10

    CPC分类号: H01L27/0203 H01L27/11807

    摘要: A semiconductor integrated circuit is provided which entails no increase in the correction time of OPC and in which non-uniformity in the gate lengths due to the optical proximity effects is surely suppressed. A plurality of standard cells (C1, C2, C3, . . . ), each including gates G extended in the vertical direction, are aligned in the transverse direction to form a standard cell row. A plurality of the standard cell rows are located side by side in the vertical direction to form a standard cell group. Each of the standard cell rows has a terminal standard cell Ce at least one end of the standard cell row. The terminal standard cell Ce includes two or more supplementary gates, each of which is any of a dummy gate and a gate of an inactive transistor.

    摘要翻译: 提供了一种半导体集成电路,其不需要增加OPC的校正时间,并且可靠地抑制由于光学邻近效应引起的栅极长度的不均匀性。 在垂直方向上延伸的包括栅极G的多个标准单元(C 1,C 2,C 3,...)在横向方向上排列以形成标准单元行。 多个标准单元行在垂直方向上并排设置以形成标准单元组。 每个标准单元行在标准单元行的至少一端具有端子标准单元Ce。 终端标准单元Ce包括两个或更多个辅助栅极,每个补充栅极是无源晶体管的伪栅极和栅极中的任一个。

    Semiconductor device and layout design method for the same
    4.
    发明申请
    Semiconductor device and layout design method for the same 有权
    半导体器件和布局设计方法相同

    公开(公告)号:US20060181309A1

    公开(公告)日:2006-08-17

    申请号:US11354936

    申请日:2006-02-16

    IPC分类号: H03K19/177

    CPC分类号: H01L27/0207 H01L27/11807

    摘要: A rectangular opening is formed in a power supply line which is shared between cell rows. A connection to a substrate potential supply line is ensured in the rectangular opening.

    摘要翻译: 在单元列之间共享的电源线中形成矩形开口。 在矩形开口中确保与衬底电位供给线的连接。

    Method of forming a nitride or carbonitride layer
    5.
    发明授权
    Method of forming a nitride or carbonitride layer 失效
    形成氮化物或碳氮化物层的方法

    公开(公告)号:US5443662A

    公开(公告)日:1995-08-22

    申请号:US84322

    申请日:1993-06-30

    CPC分类号: C23C16/442

    摘要: A nitride or carbonitride layer is formed on the surface of a metal material as follows: A treating agent composed of a refractory powder of alumina or the like and a powder of a metal for forming a nitride or a carbide or an alloy thereof is disposed in a fluidized bed furnace; the treating agent is fluidized to form a fluidized bed by introducing an inert gas; the fluidized bed furnace is heated to a temperature of not higher than 700.degree. C.; an activator of a halogenated ammonium salt is intermittently supplied into the fluidized bed at a rate of 0.001 to 5 wt %/hour based on the total amount of the treating agent; and the metal material to be treated is disposed in the fluidized bed during or after any of the above steps. For example, a nitride layer composed of only a metal for forming a nitride which contains almost no Fe--N is formed on the surface of iron steel even at a temperature as low as not higher than 700.degree. C. The layer is very hard and efficient in wear resistance, and the toughness of the base metal is hardly lowered.

    摘要翻译: 在金属材料的表面上如下形成氮化物或碳氮化物层:由氧化铝等的耐火材料粉末和用于形成氮化物的金属粉末或其合金构成的处理剂设置在 流化床炉; 通过引入惰性气体使处理剂流化形成流化床; 将流化床炉加热至不高于700℃的温度; 基于处理剂的总量,以0.001至5重量%/小时的速率将卤化铵盐的活化剂间歇地供给到流化床中; 并且在任何上述步骤期间或之后将要处理的金属材料设置在流化床中。 例如,即使在700℃以下的温度下,也在铁钢的表面上形成仅由形成几乎不含Fe-N的氮化物的金属构成的氮化物层。该层非常硬, 耐磨损性高,贱金属的韧性几乎不降低。

    Method and apparatus for forming film
    6.
    发明授权
    Method and apparatus for forming film 有权
    薄膜成膜方法及装置

    公开(公告)号:US08652587B2

    公开(公告)日:2014-02-18

    申请号:US13046208

    申请日:2011-03-11

    IPC分类号: H05H1/24

    摘要: This invention adopts plasma-enhanced chemical vapor deposition using the apparatus including a chamber, a pair of rotary electrode reels including a feed-out reel and a take-up reel, a plasma source, a material gas supplier, and an exhaust unit, and includes applying a negative voltage applied to the rotary electrode reels from the plasma source while a conductive substrate is fed-out from the feed-out reel and is wound on the take-up reel so that the entire surface of the substrate portion between reels contacts the material gas, whereby plasma sheath is formed along the surface of the substrate portion between reels, and the material gas is activated in the plasma sheath and thus contacts the surface of the substrate, thus forming the film on the surface of the substrate.

    摘要翻译: 本发明采用等离子体增强化学气相沉积法,该装置包括一个室,一对旋转电极卷轴,包括一个送出卷轴和一个卷取卷轴,等离子体源,原料气体供应器和排气单元,以及 包括在从所述送出卷轴送出导电性基板并卷绕在所述卷取卷轴上时,施加从所述等离子体源施加到所述旋转电极卷轴上的负电压,使得所述基板部分在卷盘接触之间的整个表面 材料气体,由此在卷轴之间沿着基板部分的表面形成等离子体护套,并且材料气体在等离子体护套中被激活,并且因此接触基板的表面,从而在基板的表面上形成膜。

    SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE
    10.
    发明申请
    SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 有权
    半导体集成电路设备

    公开(公告)号:US20100001404A1

    公开(公告)日:2010-01-07

    申请号:US12542263

    申请日:2009-08-17

    IPC分类号: H01L23/52

    摘要: A layout structure of a semiconductor integrated circuit is provided with which narrowing and breaking of metal interconnects near a cell boundary can be prevented without increasing the data amount and processing time for OPC. A cell A and a cell B are adjacent to each other along a cell boundary. The interconnect regions of metal interconnects from which to the cell boundary no other interconnect region exists are placed to be substantially axisymmetric with respect to the cell boundary, while sides of diffusion regions facing the cell boundary are asymmetric with respect to the cell boundary.

    摘要翻译: 提供半导体集成电路的布局结构,可以防止在单元边界附近的金属互连的变窄和断开,而不增加OPC的数据量和处理时间。 单元格A和单元格B沿着单元边界彼此相邻。 相对于单元边界,金属互连的连接区域与单元边界不存在其他互连区域被放置为基本上是轴对称的,而面向单元边界的扩散区域的边相对于单元边界是不对称的。