利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

6 条记录 (耗时 0.021 秒)

    Method of Exposing Circuit Lateral Interconnect Contacts by Wafer Saw
    3.
    发明申请
    Method of Exposing Circuit Lateral Interconnect Contacts by Wafer Saw 有权
    通过晶片锯暴露电路横向互连触点的方法

    公开(公告)号：US20090029526A1

    公开(公告)日：2009-01-29

    申请号：US11782488

    申请日：2007-07-24

    申请人： Patty Pei-Ling Chang-Chien ,  Kelly Jill Tornquist Hennig ,  Ken Wai-Kin Ho ,  Ann Kent-Ming Ho

    发明人： Patty Pei-Ling Chang-Chien ,  Kelly Jill Tornquist Hennig ,  Ken Wai-Kin Ho ,  Ann Kent-Ming Ho

    IPC分类号： H01L21/00

    CPC分类号： B81B7/007 ,  B81B2201/0271 ,  B81C2203/0118 ,  H01L23/10 ,  H01L2924/0002 ,  H01L2924/01079 ,  H01L2924/1423 ,  H01L2924/3011 ,  H01L2924/00

    摘要： A method for fabricating wafer-level packages including lateral interconnects. The method includes precutting a cover wafer at the locations where the cover wafer will be completely cut through to separate the wafer-level packages. The cover wafer is bonded to the substrate wafer using bonding rings so as to seal the integrated circuit within a cavity between the cover wafer and the substrate wafer, where the precuts face the substrate wafer. The cover wafer is then cut at the precut locations to remove the unwanted portions of the cover wafer between the packages and expose contacts or probe pads for the lateral interconnects. The substrate wafer is then cut between the wafer-level packages to separate the packages.

    摘要翻译： 一种用于制造包括横向互连的晶片级封装件的方法。 该方法包括在覆盖晶片将被完全切割穿过的位置处去除覆盖晶片以分离晶片级封装。 覆盖晶片使用接合环结合到基板晶片，以便将集成电路密封在盖晶片和基板晶片之间的空腔内，其中预切线面对基板晶片。 然后在预切割位置切割覆盖晶片以去除封装之间的覆盖晶片的不需要的部分，并暴露用于横向互连的触点或探针焊盘。 然后在晶片级封装之间切割衬底晶片以分离封装。

    Method of exposing circuit lateral interconnect contacts by wafer saw
    4.
    发明授权
    Method of exposing circuit lateral interconnect contacts by wafer saw 有权
    通过晶片锯暴露电路横向互连触点的方法

    公开(公告)号：US07662669B2

    公开(公告)日：2010-02-16

    申请号：US11782488

    申请日：2007-07-24

    申请人： Patty Pei-Ling Chang-Chien ,  Kelly Jill Tornquist Hennig ,  Ken Wai-Kin Ho ,  Ann Kent-Ming Ho

    发明人： Patty Pei-Ling Chang-Chien ,  Kelly Jill Tornquist Hennig ,  Ken Wai-Kin Ho ,  Ann Kent-Ming Ho

    IPC分类号： H01L21/00

    CPC分类号： B81B7/007 ,  B81B2201/0271 ,  B81C2203/0118 ,  H01L23/10 ,  H01L2924/0002 ,  H01L2924/01079 ,  H01L2924/1423 ,  H01L2924/3011 ,  H01L2924/00

    摘要： A method for fabricating wafer-level packages including lateral interconnects. The method includes precutting a cover wafer at the locations where the cover wafer will be completely cut through to separate the wafer-level packages. The cover wafer is bonded to the substrate wafer using bonding rings so as to seal the integrated circuit within a cavity between the cover wafer and the substrate wafer, where the precuts face the substrate wafer. The cover wafer is then cut at the precut locations to remove the unwanted portions of the cover wafer between the packages and expose contacts or probe pads for the lateral interconnects. The substrate wafer is then cut between the wafer-level packages to separate the packages.

    摘要翻译： 一种用于制造包括横向互连的晶片级封装件的方法。 该方法包括在覆盖晶片将被完全切割穿过的位置处去除覆盖晶片以分离晶片级封装。 覆盖晶片使用接合环结合到基板晶片，以便将集成电路密封在盖晶片和基板晶片之间的空腔内，其中预切线面对基板晶片。 然后在预切割位置切割覆盖晶片以去除封装之间的覆盖晶片的不需要的部分，并暴露横向互连的触点或探针焊盘。 然后在晶片级封装之间切割衬底晶片以分离封装。

    Support structures for on-wafer testing of wafer-level packages and multiple wafer stacked structures
    5.
    发明授权
    Support structures for on-wafer testing of wafer-level packages and multiple wafer stacked structures 有权
    用于晶圆级封装和多晶圆堆叠结构的片上测试的支撑结构

    公开(公告)号：US07919839B2

    公开(公告)日：2011-04-05

    申请号：US11782497

    申请日：2007-07-24

    申请人： Patty Pei-Ling Chang-Chien ,  Kelly Jill Tornquist Hennig

    发明人： Patty Pei-Ling Chang-Chien ,  Kelly Jill Tornquist Hennig

    IPC分类号： H01L23/02

    CPC分类号： H01L23/10 ,  H01L2924/0002 ,  H01L2924/01079 ,  H01L2924/1423 ,  H01L2924/00

    摘要： A semiconductor structure, such as a wafer-level package or a vertically stacked structure. The wafer-level package includes a substrate wafer on which an integrated circuit is formed. A cover wafer is bonded to the substrate wafer to provide a cavity between the substrate wafer and the cover wafer in which the integrated circuit is hermetically sealed. Vias are formed through the substrate wafer and make electrical contact with signal and ground traces formed on the substrate wafer within the cavity, where the traces are electrically coupled to the integrated circuit. Probe pads are formed on the substrate wafer outside of the cavity and are in electrical contact with the vias. A support post is provided directly beneath the probe pad so that when pressure is applied to the probe pad from the probe for testing purposes, the support post prevents the substrate wafer from flexing and being damaged.

    摘要翻译： 诸如晶片级封装或垂直堆叠结构的半导体结构。 晶片级封装包括其上形成有集成电路的衬底晶片。 覆盖晶片结合到衬底晶片以在衬底晶片和盖晶片之间提供空腔，其中集成电路被气密密封。 通过衬底晶片形成通孔，并与腔内的衬底晶片上形成的信号和接地迹线进行电接触，其中迹线电耦合到集成电路。 探针焊盘形成在空腔外部的衬底晶片上，并且与通孔电接触。 支撑柱直接设置在探针垫的正下方，因此当用于测试目的的压力从探针施加到探针垫时，支撑柱防止基底晶片弯曲并损坏。

    Support Structures for On-Wafer Testing of Wafer-Level Packages and Multiple Wafer Stacked Structures
    6.
    发明申请
    Support Structures for On-Wafer Testing of Wafer-Level Packages and Multiple Wafer Stacked Structures 有权
    晶圆级封装和多晶圆堆叠结构的片上测试支持结构

    公开(公告)号：US20090026627A1

    公开(公告)日：2009-01-29

    申请号：US11782497

    申请日：2007-07-24

    申请人： Patty Pei-Ling Chang-Chien ,  Kelly Jill Tornquist Hennig

    发明人： Patty Pei-Ling Chang-Chien ,  Kelly Jill Tornquist Hennig

    IPC分类号： H01L23/02 ,  H01L21/683

    CPC分类号： H01L23/10 ,  H01L2924/0002 ,  H01L2924/01079 ,  H01L2924/1423 ,  H01L2924/00

    摘要： A semiconductor structure, such as a wafer-level package or a vertically stacked structure. The wafer-level package includes a substrate wafer on which an integrated circuit is formed. A cover wafer is bonded to the substrate wafer to provide a cavity between the substrate wafer and the cover wafer in which the integrated circuit is hermetically sealed. Vias are formed through the substrate wafer and make electrical contact with signal and ground traces formed on the substrate wafer within the cavity, where the traces are electrically coupled to the integrated circuit. Probe pads are formed on the substrate wafer outside of the cavity and are in electrical contact with the vias. A support post is provided directly beneath the probe pad so that when pressure is applied to the probe pad from the probe for testing purposes, the support post prevents the substrate wafer from flexing and being damaged.

    摘要翻译： 诸如晶片级封装或垂直堆叠结构的半导体结构。 晶片级封装包括其上形成有集成电路的衬底晶片。 覆盖晶片结合到衬底晶片以在衬底晶片和盖晶片之间提供空腔，其中集成电路被气密密封。 通过衬底晶片形成通孔，并与腔内的衬底晶片上形成的信号和接地迹线进行电接触，其中迹线电耦合到集成电路。 探针焊盘形成在空腔外部的衬底晶片上，并且与通孔电接触。 支撑柱直接设置在探针垫的正下方，因此当用于测试目的的压力被从探针施加到探针垫时，支撑柱防止基底晶片弯曲并损坏。