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公开(公告)号：US07662669B2
公开(公告)日：2010-02-16
申请号：US11782488
申请日：2007-07-24
IPC分类号： H01L21/00
CPC分类号： B81B7/007 , B81B2201/0271 , B81C2203/0118 , H01L23/10 , H01L2924/0002 , H01L2924/01079 , H01L2924/1423 , H01L2924/3011 , H01L2924/00
摘要： A method for fabricating wafer-level packages including lateral interconnects. The method includes precutting a cover wafer at the locations where the cover wafer will be completely cut through to separate the wafer-level packages. The cover wafer is bonded to the substrate wafer using bonding rings so as to seal the integrated circuit within a cavity between the cover wafer and the substrate wafer, where the precuts face the substrate wafer. The cover wafer is then cut at the precut locations to remove the unwanted portions of the cover wafer between the packages and expose contacts or probe pads for the lateral interconnects. The substrate wafer is then cut between the wafer-level packages to separate the packages.
摘要翻译： 一种用于制造包括横向互连的晶片级封装件的方法。 该方法包括在覆盖晶片将被完全切割穿过的位置处去除覆盖晶片以分离晶片级封装。 覆盖晶片使用接合环结合到基板晶片，以便将集成电路密封在盖晶片和基板晶片之间的空腔内，其中预切线面对基板晶片。 然后在预切割位置切割覆盖晶片以去除封装之间的覆盖晶片的不需要的部分，并暴露横向互连的触点或探针焊盘。 然后在晶片级封装之间切割衬底晶片以分离封装。
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公开(公告)号：US07777318B2
公开(公告)日：2010-08-17
申请号：US11782460
申请日：2007-07-24
申请人： Kelly Jill Tornquist Hennig , Patty Pei-Ling Chang-Chien , Xianglin Zeng , Jeffrey Ming-Jer Yang
发明人： Kelly Jill Tornquist Hennig , Patty Pei-Ling Chang-Chien , Xianglin Zeng , Jeffrey Ming-Jer Yang
IPC分类号： H01L23/20
CPC分类号： H01L23/26 , H01L23/053 , H01L23/10 , H01L2924/0002 , H01L2924/1423 , H01L2924/00
摘要： A wafer-level package that employs one or more integrated hydrogen getters within the wafer-level package on a substrate wafer or a cover wafer. The hydrogen getters are provided between and among the integrated circuits on the substrate wafer or the cover wafer, and are deposited during the integrated circuit fabrication process. In one non-limiting embodiment, the substrate wafer is a group III-V semiconductor material, and the hydrogen getter includes a titanium layer, a nickel layer, and a palladium layer.
摘要翻译： 晶片级封装，其在晶片级封装中在衬底晶片或覆盖晶片上采用一个或多个集成氢吸气剂。 氢吸气剂设置在衬底晶片或覆盖晶片上的集成电路之间和之间，并且在集成电路制造过程期间被沉积。 在一个非限制性实施例中，衬底晶片是III-V族半导体材料，并且吸氢剂包括钛层，镍层和钯层。
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3.发明申请Support Structures for On-Wafer Testing of Wafer-Level Packages and Multiple Wafer Stacked Structures 有权晶圆级封装和多晶圆堆叠结构的片上测试支持结构公开(公告)号：US20090026627A1
公开(公告)日：2009-01-29
申请号：US11782497
申请日：2007-07-24
IPC分类号： H01L23/02 , H01L21/683
CPC分类号： H01L23/10 , H01L2924/0002 , H01L2924/01079 , H01L2924/1423 , H01L2924/00
摘要： A semiconductor structure, such as a wafer-level package or a vertically stacked structure. The wafer-level package includes a substrate wafer on which an integrated circuit is formed. A cover wafer is bonded to the substrate wafer to provide a cavity between the substrate wafer and the cover wafer in which the integrated circuit is hermetically sealed. Vias are formed through the substrate wafer and make electrical contact with signal and ground traces formed on the substrate wafer within the cavity, where the traces are electrically coupled to the integrated circuit. Probe pads are formed on the substrate wafer outside of the cavity and are in electrical contact with the vias. A support post is provided directly beneath the probe pad so that when pressure is applied to the probe pad from the probe for testing purposes, the support post prevents the substrate wafer from flexing and being damaged.
摘要翻译： 诸如晶片级封装或垂直堆叠结构的半导体结构。 晶片级封装包括其上形成有集成电路的衬底晶片。 覆盖晶片结合到衬底晶片以在衬底晶片和盖晶片之间提供空腔，其中集成电路被气密密封。 通过衬底晶片形成通孔，并与腔内的衬底晶片上形成的信号和接地迹线进行电接触，其中迹线电耦合到集成电路。 探针焊盘形成在空腔外部的衬底晶片上，并且与通孔电接触。 支撑柱直接设置在探针垫的正下方，因此当用于测试目的的压力被从探针施加到探针垫时，支撑柱防止基底晶片弯曲并损坏。
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公开(公告)号：US20090029526A1
公开(公告)日：2009-01-29
申请号：US11782488
申请日：2007-07-24
IPC分类号： H01L21/00
CPC分类号： B81B7/007 , B81B2201/0271 , B81C2203/0118 , H01L23/10 , H01L2924/0002 , H01L2924/01079 , H01L2924/1423 , H01L2924/3011 , H01L2924/00
摘要： A method for fabricating wafer-level packages including lateral interconnects. The method includes precutting a cover wafer at the locations where the cover wafer will be completely cut through to separate the wafer-level packages. The cover wafer is bonded to the substrate wafer using bonding rings so as to seal the integrated circuit within a cavity between the cover wafer and the substrate wafer, where the precuts face the substrate wafer. The cover wafer is then cut at the precut locations to remove the unwanted portions of the cover wafer between the packages and expose contacts or probe pads for the lateral interconnects. The substrate wafer is then cut between the wafer-level packages to separate the packages.
摘要翻译： 一种用于制造包括横向互连的晶片级封装件的方法。 该方法包括在覆盖晶片将被完全切割穿过的位置处去除覆盖晶片以分离晶片级封装。 覆盖晶片使用接合环结合到基板晶片，以便将集成电路密封在盖晶片和基板晶片之间的空腔内，其中预切线面对基板晶片。 然后在预切割位置切割覆盖晶片以去除封装之间的覆盖晶片的不需要的部分，并暴露用于横向互连的触点或探针焊盘。 然后在晶片级封装之间切割衬底晶片以分离封装。
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5.发明授权Support structures for on-wafer testing of wafer-level packages and multiple wafer stacked structures 有权用于晶圆级封装和多晶圆堆叠结构的片上测试的支撑结构公开(公告)号：US07919839B2
公开(公告)日：2011-04-05
申请号：US11782497
申请日：2007-07-24
IPC分类号： H01L23/02
CPC分类号： H01L23/10 , H01L2924/0002 , H01L2924/01079 , H01L2924/1423 , H01L2924/00
摘要： A semiconductor structure, such as a wafer-level package or a vertically stacked structure. The wafer-level package includes a substrate wafer on which an integrated circuit is formed. A cover wafer is bonded to the substrate wafer to provide a cavity between the substrate wafer and the cover wafer in which the integrated circuit is hermetically sealed. Vias are formed through the substrate wafer and make electrical contact with signal and ground traces formed on the substrate wafer within the cavity, where the traces are electrically coupled to the integrated circuit. Probe pads are formed on the substrate wafer outside of the cavity and are in electrical contact with the vias. A support post is provided directly beneath the probe pad so that when pressure is applied to the probe pad from the probe for testing purposes, the support post prevents the substrate wafer from flexing and being damaged.
摘要翻译： 诸如晶片级封装或垂直堆叠结构的半导体结构。 晶片级封装包括其上形成有集成电路的衬底晶片。 覆盖晶片结合到衬底晶片以在衬底晶片和盖晶片之间提供空腔，其中集成电路被气密密封。 通过衬底晶片形成通孔，并与腔内的衬底晶片上形成的信号和接地迹线进行电接触，其中迹线电耦合到集成电路。 探针焊盘形成在空腔外部的衬底晶片上，并且与通孔电接触。 支撑柱直接设置在探针垫的正下方，因此当用于测试目的的压力从探针施加到探针垫时，支撑柱防止基底晶片弯曲并损坏。
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公开(公告)号：US20090026598A1
公开(公告)日：2009-01-29
申请号：US11782460
申请日：2007-07-24
申请人： Kelly Jill Tornquist Hennig , Patty Pei-Ling Chang-Chien , Xianglin Zeng , Jeffrey Ming-Jer Yang
发明人： Kelly Jill Tornquist Hennig , Patty Pei-Ling Chang-Chien , Xianglin Zeng , Jeffrey Ming-Jer Yang
CPC分类号： H01L23/26 , H01L23/053 , H01L23/10 , H01L2924/0002 , H01L2924/1423 , H01L2924/00
摘要： A wafer-level package that employs one or more integrated hydrogen getters within the wafer-level package on a substrate wafer or a cover wafer. The hydrogen getters are provided between and among the integrated circuits on the substrate wafer or the cover wafer, and are deposited during the integrated circuit fabrication process. In one non-limiting embodiment, the substrate wafer is a group III-V semiconductor material, and the hydrogen getter includes a titanium layer, a nickel layer, and a palladium layer.
摘要翻译： 晶片级封装，其在晶片级封装中在衬底晶片或覆盖晶片上采用一个或多个集成氢吸气剂。 氢吸气剂设置在衬底晶片或覆盖晶片上的集成电路之间和之间，并且在集成电路制造过程期间被沉积。 在一个非限制性实施例中，衬底晶片是III-V族半导体材料，并且吸氢剂包括钛层，镍层和钯层。
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公开(公告)号：US08598465B2
公开(公告)日：2013-12-03
申请号：US13015132
申请日：2011-01-27
IPC分类号： H05K1/11
CPC分类号： H01L23/522 , H01L21/50 , H01L21/561 , H01L23/10 , H01L23/5329 , H01L23/552 , H01L23/585 , H01L23/66 , H01L24/80 , H01L25/0657 , H01L2223/6683 , H01L2224/94 , H01L2225/06513 , H01L2225/06537 , H01L2224/80
摘要： A wafer-scale assembly circuit including a plurality of metal interconnect layers, where each metal layer includes patterned metal portions and where at least some of the patterned metal portions are RF signal lines. The circuit further includes at least one benzocyclobutene layer provided between two metal interconnect layers that includes at least one trench via formed around a perimeter of the benzocyclobutene layer at a circuit sealing ring, where the trench via provides a hermetic seal at the sealing ring. The benzocyclobutene layer also includes a plurality of stabilizing post vias formed through the benzocyclobutene layer adjacent to the trench via proximate to the sealing ring and extending around the perimeter of the benzocyclobutene layer, where the stabilizing vias operate to prevent the benzocyclobutene layer from shrinking in size.
摘要翻译： 包括多个金属互连层的晶片级组装电路，其中每个金属层包括图案化的金属部分，并且其中至少一些图案化的金属部分是RF信号线。 该电路还包括至少一个设置在两个金属互连层之间的苯并环丁烯层，其包括在电路密封环处围绕苯并环丁烯层的周边形成的至少一个沟槽通道，其中沟槽通孔在密封环处提供气密密封。 苯并环丁烯层还包括多个稳定的通孔，其通过邻近密封环的邻近沟槽的苯并环丁烯层形成，并且围绕苯并环丁烯层的周边延伸，其中稳定通孔的作用是防止苯并环丁烯层的尺寸收缩 。
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公开(公告)号：US07696062B2
公开(公告)日：2010-04-13
申请号：US11828147
申请日：2007-07-25
IPC分类号： H01L21/30
CPC分类号： H01L23/66 , H01L21/6835 , H01L21/6836 , H01L25/16 , H01L2221/68327 , H01L2223/6677 , H01L2224/16145 , H01L2224/94 , H01L2924/0002 , H01L2924/1423 , H01Q1/38 , H01L2924/00 , H01L2224/81
摘要： A method for mounting a dielectric substrate to a semiconductor substrate, such as mounting a dielectric antenna substrate to an MMIC semiconductor substrate. The method includes providing a thin dielectric antenna substrate having metallized layers on opposing sides. In one embodiment, carrier wafers are used to handle and maintain the dielectric substrate in a flat configuration as the metallized layers are patterned. The dielectric substrate is sealed to the semiconductor substrate using a low temperature bonding process. In an alternate embodiment, the metallized layers on the dielectric substrate are patterned simultaneously so as to prevent the substrate from curling.
摘要翻译： 将电介质基板安装到半导体基板上的方法，例如将电介质天线基板安装到MMIC半导体基板上。 该方法包括提供在相对侧上具有金属化层的薄介电天线基板。 在一个实施例中，当金属化层被图案化时，载体晶片用于处理和维持电介质基板处于平坦配置。 使用低温接合工艺将电介质基板密封到半导体基板。 在替代实施例中，电介质基板上的金属化层被同时图案化，以防止基板卷曲。
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9.发明授权Monolithically integrated active electronic circuit and waveguide structure for terahertz frequencies 有权用于太赫兹频率的单片集成有源电子电路和波导结构公开(公告)号：US08686813B2
公开(公告)日：2014-04-01
申请号：US12584075
申请日：2009-08-29
申请人： William Roland Deal , Kevin Masaru Kung Hoong Leong , Vesna Radisic , Patty Pei-Ling Chang-Chien , Richard Lai
发明人： William Roland Deal , Kevin Masaru Kung Hoong Leong , Vesna Radisic , Patty Pei-Ling Chang-Chien , Richard Lai
CPC分类号： G02B6/10 , H01L23/66 , H01L2223/6627 , H01L2223/6677 , H01L2924/0002 , H01L2924/00
摘要： An electronic system. The electronic system includes a waveguide structure having a first waveguide-coupling point and a second waveguide-coupling point and an active electronic circuit having a first circuit-coupling point and a second circuit-coupling point. The second waveguide-coupling point is coupled to the first circuit-coupling point; the system is capable of receiving an input signal at the first waveguide-coupling point and transmitting an output signal at the second circuit-coupling point and/or receiving the input signal at the second circuit-coupling point and transmitting the output signal at the first waveguide-coupling point; the input signal and the output signal have frequencies in a terahertz frequency range; and the system is fabricated as a monolithic integrated structure having the waveguide structure fabricated by micromachining and the circuit fabricated monolithically.
摘要翻译： 电子系统。 电子系统包括具有第一波导耦合点和第二波导耦合点的波导结构以及具有第一电路耦合点和第二电路耦合点的有源电子电路。 第二波导耦合点耦合到第一电路耦合点; 该系统能够在第一波导耦合点处接收输入信号，并在第二电路耦合点处传输输出信号和/或在第二电路耦合点处接收输入信号，并在第一电路耦合点处发送输出信号 波导耦合点; 输入信号和输出信号具有在太赫兹频率范围内的频率; 并且该系统被制造为具有通过微加工制造的波导结构和整体制造的电路的单片集成结构。
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10.发明申请Monolithically integrated active electronic circuit and waveguide structure for terahertz frequencies 有权用于太赫兹频率的单片集成有源电子电路和波导结构公开(公告)号：US20110050371A1
公开(公告)日：2011-03-03
申请号：US12584075
申请日：2009-08-29
申请人： William Roland Deal , Kevin Masaru Kung Hoong Leong , Vesna Radisic , Patty Pei-Ling Chang-Chien , Richard Lai
发明人： William Roland Deal , Kevin Masaru Kung Hoong Leong , Vesna Radisic , Patty Pei-Ling Chang-Chien , Richard Lai
CPC分类号： G02B6/10 , H01L23/66 , H01L2223/6627 , H01L2223/6677 , H01L2924/0002 , H01L2924/00
摘要： An electronic system. The electronic system includes a waveguide structure having a first waveguide-coupling point and a second waveguide-coupling point and an active electronic circuit having a first circuit-coupling point and a second circuit-coupling point. The second waveguide-coupling point is coupled to the first circuit-coupling point; the system is capable of receiving an input signal at the first waveguide-coupling point and transmitting an output signal at the second circuit-coupling point and/or receiving the input signal at the second circuit-coupling point and transmitting the output signal at the first waveguide-coupling point; the input signal and the output signal have frequencies in a terahertz frequency range; and the system is fabricated as a monolithic integrated structure having the waveguide structure fabricated by micromachining and the circuit fabricated monolithically.
摘要翻译： 电子系统。 电子系统包括具有第一波导耦合点和第二波导耦合点的波导结构以及具有第一电路耦合点和第二电路耦合点的有源电子电路。 第二波导耦合点耦合到第一电路耦合点; 该系统能够在第一波导耦合点处接收输入信号，并在第二电路耦合点处传输输出信号和/或在第二电路耦合点处接收输入信号，并在第一电路耦合点处发送输出信号 波导耦合点; 输入信号和输出信号具有在太赫兹频率范围内的频率; 并且该系统被制造为具有通过微加工制造的波导结构和整体制造的电路的单片集成结构。
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