公开(公告)号：US5801561A

公开(公告)日：1998-09-01

申请号：US842501

申请日：1997-04-21

申请人： Keng L. Wong ,  Gregory F. Taylor ,  Roshan J. Fernando ,  Jeffrey E. Smith

发明人： Keng L. Wong ,  Gregory F. Taylor ,  Roshan J. Fernando ,  Jeffrey E. Smith

IPC分类号： H03K17/22

CPC分类号： H03K17/22

摘要： A method and apparatus for reducing contention in an integrated circuit during power-up. According to one aspect of the invention, an initialization circuit is included in an integrated circuit. In response to receiving Vcc, the initialization circuit generates a substitute clock signal and a substitute reset signal. The substitute clock signal and substitute reset signal are substituted for an off chip generated clock signal and an off chip generated reset signal during power-up until a predetermined condition is met. In response to receiving the substitute clock signal and the substitute reset signal, a plurality of circuits on said integrated circuit are initialized.

摘要翻译： 一种减少上电期间集成电路竞争的方法和装置。 根据本发明的一个方面，在集成电路中包括初始化电路。 响应于接收到Vcc，初始化电路产生替代时钟信号和替代复位信号。 替代时钟信号和替代复位信号在上电期间代替芯片内产生的时钟信号和芯片外产生的复位信号，直到满足预定条件。 响应于接收到替代时钟信号和替代复位信号，初始化所述集成电路上的多个电路。

公开(公告)号：US5557225A

公开(公告)日：1996-09-17

申请号：US367103

申请日：1994-12-30

申请人： Martin S. Denham ,  Keng L. Wong ,  Jeffrey E. Smith ,  Roshan J. Fernando

发明人： Martin S. Denham ,  Keng L. Wong ,  Jeffrey E. Smith ,  Roshan J. Fernando

IPC分类号： H03K3/037

CPC分类号： H03K3/037

摘要： A flip-flop circuit is described. The flip-flop circuit receives the data signal from a data input, receives a trigger signal from a trigger input, generates a pulse signal in response to an edge in the trigger signal, and stores the data signal in response to the pulse. Alternatively, the flip-flop circuit receives a data signal through a data input, receives a trigger signal through a trigger input, stores the data signal in a latch, and suppresses the trigger signal to the latch when the data signal stored in the latch corresponds to the data signal received through the data input.

摘要翻译： 描述触发器电路。 触发器电路从数据输入接收数据信号，从触发输入接收触发信号，响应于触发信号中的边缘产生脉冲信号，并响应脉冲存储数据信号。 或者，触发器电路通过数据输入接收数据信号，通过触发输入接收触发信号，将数据信号存储在锁存器中，并且当存储在锁存器中的数据信号对应于锁存器时，将触发信号抑制到锁存器 到通过数据输入接收的数据信号。

公开(公告)号：US5931930A

公开(公告)日：1999-08-03

申请号：US723667

申请日：1996-09-30

申请人： Robert F. Krick ,  Roshan J. Fernando

发明人： Robert F. Krick ,  Roshan J. Fernando

IPC分类号： G06F15/16 ,  G06F9/52 ,  G06F13/24 ,  G06F15/177 ,  G06F13/00 ,  G06F9/46 ,  G06F15/00

CPC分类号： G06F13/24

摘要： A computer system is disclosed having a processor with a type input pin that indicates whether the processor is coupled as an OEM processor a single processor or a dual processor computer system or as an upgrade processor in the dual processor computer system. The processor includes an upgrade/OEM output pin coupled to transfer an upgrade/OEM signal over a system bus if the type input pin indicates the OEM processor. The upgrade/OEM signal indicates whether the OEM processor or the upgrade processor is a bus owner of the system bus.

摘要翻译： 公开了一种具有处理器的计算机系统，该处理器具有类型输入引脚，其指示该处理器是否作为OEM处理器耦合到单处理器或双处理器计算机系统，或作为双处理器计算机系统中的升级处理器。 处理器包括升级/ OEM输出引脚，如果类型输入引脚指示OEM处理器，则该引脚耦合以通过系统总线传输升级/ OEM信号。 升级/ OEM信号指示OEM处理器或升级处理器是系统总线的总线所有者。

公开(公告)号：US5490279A

公开(公告)日：1996-02-06

申请号：US065597

申请日：1993-05-21

申请人： Adalberto Golbert ,  Douglas M. Carean ,  Roshan J. Fernando ,  Amar A. Ghori ,  Yoav Hochberg ,  Robert F. Krick ,  Milind Mittal ,  Anurag Sah

发明人： Adalberto Golbert ,  Douglas M. Carean ,  Roshan J. Fernando ,  Amar A. Ghori ,  Yoav Hochberg ,  Robert F. Krick ,  Milind Mittal ,  Anurag Sah

IPC分类号： G06F15/177 ,  G06F9/38 ,  G06F13/40 ,  G06F15/167 ,  G06F3/00 ,  G06F15/17

CPC分类号： G06F9/3879 ,  G06F13/4068 ,  G06F15/167

摘要： A method and apparatus for upgrading a uniprocessor system to a multiprocessing system simply by the insertion of a second microprocessor integrated circuit. The computer system is provided with an upgrade socket for receiving the second processing unit, as well as a private communications bus between the upgrade socket and the existing processor for handling interprocessor communications, bus arbitration and cache coherency, etc. The addition of the second processor is transparent to the system which maintains its memory management unit and caching system and other arrangements as though it were still a uniprocessing system. Therefore, an inexpensive method and apparatus are provided for greatly enhancing the speed of a uniprocessing system to that of a multiprocessing system without the cost traditionally associated with multiprocessing systems.

摘要翻译： 一种仅通过插入第二微处理器集成电路将单处理器系统升级到多处理系统的方法和装置。 计算机系统具有用于接收第二处理单元的升级插座，以及升级插座和现有处理器之间的专用通信总线，用于处理处理器间通信，总线仲裁和高速缓存一致性等。第二处理器 对系统来说是透明的，该系统保持其内存管理单元和缓存系统以及其他安排，就像它仍然是一个单处理系统一样。 因此，提供了一种便宜的方法和装置，用于大大提高单处理系统与多处理系统的速度，而无需传统上与多处理系统相关联的成本。