公开(公告)号：US20080211056A1

公开(公告)日：2008-09-04

申请号：US11978686

申请日：2007-10-30

申请人： Kenichi Kuroda ,  Kozo Watanabe ,  Hirohlko Yamamoto

发明人： Kenichi Kuroda ,  Kozo Watanabe ,  Hirohlko Yamamoto

IPC分类号： H01L29/00

CPC分类号： H01L23/5283 ,  H01L21/31053 ,  H01L21/74 ,  H01L21/76224 ,  H01L21/76229 ,  H01L23/522 ,  H01L23/528 ,  H01L23/53228 ,  H01L27/0207 ,  H01L27/11807 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0692 ,  H01L29/4925 ,  H01L2924/0002 ,  H01L2924/00

摘要： There is provided a technique for improving the flatness at the surface of members embedded in a plurality of recesses without resulting in an increase in the time required for the manufacturing processes. According to this technique, the dummy patterns can be placed up to the area near the boundary BL between the element forming region DA and dummy region FA by placing the first dummy pattern DP1 of relatively wider area and the second dummy pattern DP2 of relatively small area in the dummy region FA. Thereby, the flatness of the surface of the silicon oxide film embedded within the isolation groove can be improved over the entire part of the dummy region FA. Moreover, an increase of the mask data can be controlled when the first dummy patterns DP1 occupy a relatively wide region among the dummy region FA.

摘要翻译： 提供了一种用于改善嵌入在多个凹部中的构件的表面处的平坦度而不导致制造过程所需时间增加的技术。 根据该技术，可以通过放置相对较宽区域的第一虚拟图案DP 1，将虚拟图案放置在元件形成区域DA和虚拟区域FA之间的边界BL附近的区域，并且 在虚拟区域FA中具有相对较小面积的第二虚拟图案DP 2 2 。 由此，可以在虚拟区域FA的整个部分改善嵌入在隔离槽内的氧化硅膜的表面的平坦度。 此外，当虚拟区域FA中的第一伪图案DP 1占据相对较宽的区域时，可以控制掩模数据的增加。

公开(公告)号：US20120126360A1

公开(公告)日：2012-05-24

申请号：US13362385

申请日：2012-01-31

申请人： Kenichi KURODA ,  Kozo Watanabe ,  Hirohiko Yamamoto

发明人： Kenichi KURODA ,  Kozo Watanabe ,  Hirohiko Yamamoto

IPC分类号： H01L29/06

CPC分类号： H01L23/5283 ,  H01L21/31053 ,  H01L21/74 ,  H01L21/76224 ,  H01L21/76229 ,  H01L23/522 ,  H01L23/528 ,  H01L23/53228 ,  H01L27/0207 ,  H01L27/11807 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0692 ,  H01L29/4925 ,  H01L2924/0002 ,  H01L2924/00

摘要： There is provided a technique for improving the flatness at the surface of members embedded in a plurality of recesses without resulting in an increase in the time required for the manufacturing processes. According to this technique, the dummy patterns can be placed up to the area near the boundary BL between the element forming region DA and dummy region FA by placing the first dummy pattern DP1 of relatively wider area and the second dummy pattern DP2 of relatively small area in the dummy region FA. Thereby, the flatness of the surface of the silicon oxide film embedded within the isolation groove can be improved over the entire part of the dummy region FA. Moreover, an increase of the mask data can be controlled when the first dummy patterns DP1 occupy a relatively wide region among the dummy region FA.

摘要翻译： 提供了一种用于改善嵌入在多个凹部中的构件的表面处的平坦度而不导致制造过程所需时间增加的技术。 根据该技术，通过将相对较宽区域的第一伪图案DP1和相对较小面积的第二虚设图案DP2放置在元件形成区域DA和虚拟区域FA之间的边界BL附近的虚拟图案， 在虚拟区域FA中。 由此，可以在虚拟区域FA的整个部分改善嵌入在隔离槽内的氧化硅膜的表面的平坦度。 此外，当第一伪图案DP1占据虚拟区域FA中相对较宽的区域时，可以控制掩模数据的增加。

公开(公告)号：US20110207288A1

公开(公告)日：2011-08-25

申请号：US13096246

申请日：2011-04-28

申请人： Kenichi KURODA ,  Kozo Watanabe ,  Hirohiko Yamamoto

发明人： Kenichi KURODA ,  Kozo Watanabe ,  Hirohiko Yamamoto

IPC分类号： H01L21/302

CPC分类号： H01L23/5283 ,  H01L21/31053 ,  H01L21/74 ,  H01L21/76224 ,  H01L21/76229 ,  H01L23/522 ,  H01L23/528 ,  H01L23/53228 ,  H01L27/0207 ,  H01L27/11807 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0692 ,  H01L29/4925 ,  H01L2924/0002 ,  H01L2924/00

摘要： There is provided a technique for improving the flatness at the surface of members embedded in a plurality of recesses without resulting in an increase in the time required for the manufacturing processes. According to this technique, the dummy patterns can be placed up to the area near the boundary BL between the element forming region DA and dummy region FA by placing the first dummy pattern DP1 of relatively wider area and the second dummy pattern DP2 of relatively small area in the dummy region FA. Thereby, the flatness of the surface of the silicon oxide film embedded within the isolation groove can be improved over the entire part of the dummy region FA. Moreover, an increase of the mask data can be controlled when the first dummy patterns DP1 occupy a relatively wide region among the dummy region FA.

摘要翻译： 提供了一种用于改善嵌入在多个凹部中的构件的表面处的平坦度而不导致制造过程所需时间增加的技术。 根据该技术，通过将相对较宽区域的第一伪图案DP1和相对较小面积的第二虚设图案DP2放置在元件形成区域DA和虚拟区域FA之间的边界BL附近的虚拟图案， 在虚拟区域FA中。 由此，可以在虚拟区域FA的整个部分改善嵌入在隔离槽内的氧化硅膜的表面的平坦度。 此外，当第一伪图案DP1占据虚拟区域FA中相对较宽的区域时，可以控制掩模数据的增加。

公开(公告)号：US20070222080A1

公开(公告)日：2007-09-27

申请号：US11802623

申请日：2007-05-24

申请人： Kenichi Kuroda ,  Kozo Watanabe ,  Hirohiko Yamamoto

发明人： Kenichi Kuroda ,  Kozo Watanabe ,  Hirohiko Yamamoto

IPC分类号： H01L23/48

CPC分类号： H01L23/5283 ,  H01L21/31053 ,  H01L21/74 ,  H01L21/76224 ,  H01L21/76229 ,  H01L23/522 ,  H01L23/528 ,  H01L23/53228 ,  H01L27/0207 ,  H01L27/11807 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0692 ,  H01L29/4925 ,  H01L2924/0002 ,  H01L2924/00

摘要： There is provided a technique for improving the flatness at the surface of members embedded in a plurality of recesses without resulting in an increase in the time required for the manufacturing processes. According to this technique, the dummy patterns can be placed up to the area near the boundary BL between the element forming region DA and dummy region FA by placing the first dummy pattern DP1 of relatively wider area and the second dummy pattern DP2 of relatively small area in the dummy region FA. Thereby, the flatness of the surface of the silicon oxide film embedded within the isolation groove can be improved over the entire part of the dummy region FA. Moreover, an increase of the mask data can be controlled when the first dummy patterns DP1 occupy a relatively wide region among the dummy region FA.

摘要翻译： 提供了一种用于改善嵌入在多个凹部中的构件的表面处的平坦度而不导致制造过程所需时间增加的技术。 根据该技术，可以通过放置相对较宽区域的第一虚拟图案DP 1，将虚拟图案放置在元件形成区域DA和虚拟区域FA之间的边界BL附近的区域，并且 在虚拟区域FA中具有相对较小面积的第二虚拟图案DP 2 2 。 由此，可以在虚拟区域FA的整个部分改善嵌入在隔离槽内的氧化硅膜的表面的平坦度。 此外，当虚拟区域FA中的第一伪图案DP 1占据相对较宽的区域时，可以控制掩模数据的增加。

公开(公告)号：US06506647B2

公开(公告)日：2003-01-14

申请号：US09961059

申请日：2001-09-24

申请人： Kenichi Kuroda ,  Kozo Watanabe

发明人： Kenichi Kuroda ,  Kozo Watanabe

IPC分类号： H01L218234

CPC分类号： H01L27/10894 ,  H01L21/76895 ,  H01L21/76897 ,  H01L21/823814 ,  H01L21/823835 ,  H01L27/105 ,  H01L27/10873 ,  H01L29/4941

摘要： A method for fabricating a semiconductor integrated circuit device including a memory cell of a MISFET and a capacitor element formed in a memory cell-forming region of a semiconductor substrate, and an n channel-type MISFET and a p channel-type MISFET in a peripheral circuit-forming region, including: forming a gate insulating film on a semiconductor substrate; forming a polysilicon film and a high melting metal film on the gate insulating film, patterning to form a gate electrode in a memory cell-forming region and in a peripheral circuit-forming region, respectively; removing the high melting metal film from the gate electrode of the peripheral circuit-forming region; and depositing a metal layer over the peripheral circuit-forming region, followed by thermal treatment to form a silicide film on the polysilicon film in the gate electrode and a high concentration diffusion layer of the peripheral circuit-forming region.

摘要翻译： 一种用于制造半导体集成电路器件的方法，该半导体集成电路器件包括形成在半导体衬底的存储单元形成区域中的MISFET和电容器元件的存储单元，以及外围电路中的n沟道型MISFET和ap沟道型MISFET 包括：在半导体衬底上形成栅极绝缘膜; 在栅极绝缘膜上形成多晶硅膜和高熔点金属膜，构图以分别在存储单元形成区域和外围电路形成区域中形成栅电极; 从周边电路形成区域的栅电极去除高熔点金属膜; 在外围电路形成区域上沉积金属层，然后进行热处理，以在栅电极的多晶硅膜和外围电路形成区域的高浓度扩散层上形成硅化物膜。

公开(公告)号：US08119495B2

公开(公告)日：2012-02-21

申请号：US13096246

申请日：2011-04-28

申请人： Kenichi Kuroda ,  Kozo Watanabe ,  Hirohiko Yamamoto

发明人： Kenichi Kuroda ,  Kozo Watanabe ,  Hirohiko Yamamoto

IPC分类号： H01L21/76

CPC分类号： H01L23/5283 ,  H01L21/31053 ,  H01L21/74 ,  H01L21/76224 ,  H01L21/76229 ,  H01L23/522 ,  H01L23/528 ,  H01L23/53228 ,  H01L27/0207 ,  H01L27/11807 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0692 ,  H01L29/4925 ,  H01L2924/0002 ,  H01L2924/00

摘要： There is provided a technique for improving the flatness at the surface of members embedded in a plurality of recesses without resulting in an increase in the time required for the manufacturing processes. According to this technique, the dummy patterns can be placed up to the area near the boundary BL between the element forming region DA and dummy region FA by placing the first dummy pattern DP1 of relatively wider area and the second dummy pattern DP2 of relatively small area in the dummy region FA. Thereby, the flatness of the surface of the silicon oxide film embedded within the isolation groove can be improved over the entire part of the dummy region FA. Moreover, an increase of the mask data can be controlled when the first dummy patterns DP1 occupy a relatively wide region among the dummy region FA.

摘要翻译： 提供了一种用于改善嵌入在多个凹部中的构件的表面处的平坦度而不导致制造过程所需时间增加的技术。 根据该技术，通过将相对较宽区域的第一伪图案DP1和相对较小面积的第二虚设图案DP2放置在元件形成区域DA和虚拟区域FA之间的边界BL附近的虚拟图案， 在虚拟区域FA中。 由此，可以在虚拟区域FA的整个部分改善嵌入在隔离槽内的氧化硅膜的表面的平坦度。 此外，当第一伪图案DP1占据虚拟区域FA中相对较宽的区域时，可以控制掩模数据的增加。

公开(公告)号：US07948086B2

公开(公告)日：2011-05-24

申请号：US12714596

申请日：2010-03-01

申请人： Kenichi Kuroda ,  Kozo Watanabe ,  Hirohiko Yamamoto

发明人： Kenichi Kuroda ,  Kozo Watanabe ,  Hirohiko Yamamoto

IPC分类号： H01L23/48

CPC分类号： H01L23/5283 ,  H01L21/31053 ,  H01L21/74 ,  H01L21/76224 ,  H01L21/76229 ,  H01L23/522 ,  H01L23/528 ,  H01L23/53228 ,  H01L27/0207 ,  H01L27/11807 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0692 ,  H01L29/4925 ,  H01L2924/0002 ,  H01L2924/00

摘要： There is provided a technique for improving the flatness at the surface of members embedded in a plurality of recesses without resulting in an increase in the time required for the manufacturing processes. According to this technique, the dummy patterns can be placed up to the area near the boundary BL between the element forming region DA and dummy region FA by placing the first dummy pattern DP1 of relatively wider area and the second dummy pattern DP2 of relatively small area in the dummy region FA. Thereby, the flatness of the surface of the silicon oxide film embedded within the isolation groove can be improved over the entire part of the dummy region FA. Moreover, an increase of the mask data can be controlled when the first dummy patterns DP1 occupy a relatively wide region among the dummy region FA.

摘要翻译： 提供了一种用于改善嵌入在多个凹部中的构件的表面处的平坦度而不导致制造过程所需时间增加的技术。 根据该技术，通过将相对较宽区域的第一伪图案DP1和相对较小面积的第二虚设图案DP2放置在元件形成区域DA和虚拟区域FA之间的边界BL附近的虚拟图案， 在虚拟区域FA中。 由此，可以在虚拟区域FA的整个部分改善嵌入在隔离槽内的氧化硅膜的表面的平坦度。 此外，当第一伪图案DP1占据虚拟区域FA中相对较宽的区域时，可以控制掩模数据的增加。

公开(公告)号：US07589423B2

公开(公告)日：2009-09-15

申请号：US11802623

申请日：2007-05-24

申请人： Kenichi Kuroda ,  Kozo Watanabe ,  Hirohiko Yamamoto

发明人： Kenichi Kuroda ,  Kozo Watanabe ,  Hirohiko Yamamoto

IPC分类号： H01L23/48

CPC分类号： H01L23/5283 ,  H01L21/31053 ,  H01L21/74 ,  H01L21/76224 ,  H01L21/76229 ,  H01L23/522 ,  H01L23/528 ,  H01L23/53228 ,  H01L27/0207 ,  H01L27/11807 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0692 ,  H01L29/4925 ,  H01L2924/0002 ,  H01L2924/00

摘要： There is provided a technique for improving the flatness at the surface of members embedded in a plurality of recesses without resulting in an increase in the time required for the manufacturing processes. According to this technique, the dummy patterns can be placed up to the area near the boundary BL between the element forming region DA and dummy region FA by placing the first dummy pattern DP1 of relatively wider area and the second dummy pattern DP2 of relatively small area in the dummy region FA. Thereby, the flatness of the surface of the silicon oxide film embedded within the isolation groove can be improved over the entire part of the dummy region FA. Moreover, an increase of the mask data can be controlled when the first dummy patterns DP1 occupy a relatively wide region among the dummy region FA.

摘要翻译： 提供了一种用于改善嵌入在多个凹部中的构件的表面处的平坦度而不导致制造过程所需时间增加的技术。 根据该技术，通过将相对较宽区域的第一伪图案DP1和相对较小面积的第二虚设图案DP2放置在元件形成区域DA和虚拟区域FA之间的边界BL附近的虚拟图案， 在虚拟区域FA中。 由此，可以在虚拟区域FA的整个部分改善嵌入在隔离槽内的氧化硅膜的表面的平坦度。 此外，当第一伪图案DP1占据虚拟区域FA中相对较宽的区域时，可以控制掩模数据的增加。

公开(公告)号：US07411302B2

公开(公告)日：2008-08-12

申请号：US11430983

申请日：2006-05-10

申请人： Kenichi Kuroda ,  Kozo Watanabe ,  Hirohiko Yamamoto

发明人： Kenichi Kuroda ,  Kozo Watanabe ,  Hirohiko Yamamoto

IPC分类号： H01L23/48

CPC分类号： H01L23/5283 ,  H01L21/31053 ,  H01L21/74 ,  H01L21/76224 ,  H01L21/76229 ,  H01L23/522 ,  H01L23/528 ,  H01L23/53228 ,  H01L27/0207 ,  H01L27/11807 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0692 ,  H01L29/4925 ,  H01L2924/0002 ,  H01L2924/00

摘要： There is provided a technique for improving the flatness at the surface of members embedded in a plurality of recesses without resulting in an increase in the time required for the manufacturing processes. According to this technique, the dummy patterns can be placed up to the area near the boundary BL between the element forming region DA and dummy region FA by placing the first dummy pattern DP1 of relatively wider area and the second dummy pattern DP2 of relatively small area in the dummy region FA. Thereby, the flatness of the surface of the silicon oxide film embedded within the isolation groove can be improved over the entire part of the dummy region FA. Moreover, an increase of the mask data can be controlled when the first dummy patterns DP1 occupy a relatively wide region among the dummy region FA.

公开(公告)号：US07071560B2

公开(公告)日：2006-07-04

申请号：US10748139

申请日：2003-12-31

申请人： Kenichi Kuroda ,  Kozo Watanabe ,  Hirohiko Yamamoto

发明人： Kenichi Kuroda ,  Kozo Watanabe ,  Hirohiko Yamamoto

IPC分类号： H01L23/48

CPC分类号： H01L23/5283 ,  H01L21/31053 ,  H01L21/74 ,  H01L21/76224 ,  H01L21/76229 ,  H01L23/522 ,  H01L23/528 ,  H01L23/53228 ,  H01L27/0207 ,  H01L27/11807 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0692 ,  H01L29/4925 ,  H01L2924/0002 ,  H01L2924/00

摘要： There is provided a technique for improving the flatness at the surface of members embedded in a plurality of recesses without resulting in an increase in the time required for the manufacturing processes. According to this technique, the dummy patterns can be placed up to the area near the boundary BL between the element forming region DA and dummy region FA by placing the first dummy pattern DP1 of relatively wider area and the second dummy pattern DP2 of relatively small area in the dummy region FA. Thereby, the flatness of the surface of the silicon oxide film embedded within the isolation groove can be improved over the entire part of the dummy region FA. Moreover, an increase of the mask data can be controlled when the first dummy patterns DP1 occupy a relatively wide region among the dummy region FA.