公开(公告)号：US07903013B2

公开(公告)日：2011-03-08

申请号：US12507660

申请日：2009-07-22

申请人： Kenichiro Yamaguchi ,  Atsushi Okumura ,  Mitsugu Kusunoki ,  Tomoo Murata

发明人： Kenichiro Yamaguchi ,  Atsushi Okumura ,  Mitsugu Kusunoki ,  Tomoo Murata

IPC分类号： H03M1/66

CPC分类号： H03M1/0643 ,  H01L27/0203 ,  H03M1/687 ,  H03M1/745 ,  H03M1/785 ,  Y10T307/696

摘要： Operating speed as well as output accuracy of a D-A converter is enhanced. With a semiconductor device including unit current sources, and unit current source switches, plural current source elements constituting each of the unit current sources are disposed so as to be evenly dispersed, thereby reducing errors of the current source element, dependent on distance while the unit current source switches are concentratedly disposed in a small region, thereby mitigating delay in operation, attributable to parasitic capacitance. In addition, with the semiconductor device including R2R resistance ladders, the R2R resistance ladder is provided on the positive and the negative of each of the unit current source switches, and the respective R2R resistance ladders are shorted with each other at respective nodes on a unit current source switch-by-unit current source switch basis, are rendered identical in length, thereby cancelling out a nonlinearity error attributable to wiring parasitic resistance.

摘要翻译： 提高了D-A转换器的工作速度和输出精度。 利用包括单位电流源和单位电流源开关的半导体器件，构成每个单位电流源的多个电流源元件被布置成均匀分散，从而根据距离减小电流源元件的误差，而单元 电流源开关集中地设置在较小的区域中，从而减轻了由寄生电容引起的工作延迟。 另外，对于包含R2R电阻梯的半导体装置，在每个单位电流源开关的正极和负极上设置R2R电阻梯，并且相应的R2R电阻梯在单元的相应节点处相互短路 电流源逐个电流源开关基础的长度相同，从而消除归因于布线寄生电阻的非线性误差。

公开(公告)号：US20100072821A1

公开(公告)日：2010-03-25

申请号：US12507660

申请日：2009-07-22

申请人： Kenichiro YAMAGUCHI ,  Atsushi Okumura ,  Mitsugu Kusunoki ,  Tomoo Murata

发明人： Kenichiro YAMAGUCHI ,  Atsushi Okumura ,  Mitsugu Kusunoki ,  Tomoo Murata

IPC分类号： H02J3/00

CPC分类号： H03M1/0643 ,  H01L27/0203 ,  H03M1/687 ,  H03M1/745 ,  H03M1/785 ,  Y10T307/696

摘要： Operating speed as well as output accuracy of a D-A converter is enhanced. With a semiconductor device including unit current sources, and unit current source switches, plural current source elements constituting each of the unit current sources are disposed so as to be evenly dispersed, thereby reducing errors of the current source element, dependent on distance while the unit current source switches are concentratedly disposed in a small region, thereby mitigating delay in operation, attributable to parasitic capacitance. In addition, with the semiconductor device including R2R resistance ladders, the R2R resistance ladder is provided on the positive and the negative of each of the unit current source switches, and the respective R2R resistance ladders are shorted with each other at respective nodes on a unit current source switch-by-unit current source switch basis, are rendered identical in length, thereby cancelling out a nonlinearity error attributable to wiring parasitic resistance.

摘要翻译： 提高了D-A转换器的工作速度和输出精度。 利用包括单位电流源和单位电流源开关的半导体器件，构成每个单位电流源的多个电流源元件被布置成均匀分散，从而根据距离减小电流源元件的误差，而单元 电流源开关集中地设置在较小的区域中，从而减轻了由寄生电容引起的工作延迟。 另外，对于包含R2R电阻梯的半导体装置，在每个单位电流源开关的正极和负极上设置R2R电阻梯，并且相应的R2R电阻梯在单元的相应节点处相互短路 电流源逐个电流源开关基础的长度相同，从而消除归因于布线寄生电阻的非线性误差。

公开(公告)号：US07245019B2

公开(公告)日：2007-07-17

申请号：US10647373

申请日：2003-08-26

申请人： Tomoo Murata ,  Shinobu Yabuki ,  Takeo Yamashita

发明人： Tomoo Murata ,  Shinobu Yabuki ,  Takeo Yamashita

IPC分类号： H01L23/52

CPC分类号： H01L27/118 ,  H01L23/528 ,  H01L2924/0002 ,  H01L2924/00

摘要： In a method of manufacturing a semiconductor device having a first wiring extending in a first direction and a second wiring connected to the first wiring through a connection and extending in a second direction orthogonal to the first direction, the second wiring having a surplus portion projecting from the connection in a direction opposite to the second direction, the first and second wirings are arranged such that a center of the connection is offset in the second direction from a center of the first wiring, and a projecting portion of the first wiring is disposed under the connection.

摘要翻译： 在制造具有沿第一方向延伸的第一布线的半导体器件的方法和通过连接与第一布线连接并沿与​​第一方向正交的第二方向延伸的第二布线的方法中，第二布线具有从 在与第二方向相反的方向上的连接中，第一和第二布线布置成使得连接的中心在距第一布线的中心的第二方向偏移，并且第一布线的突出部分设置在 连接。

公开(公告)号：US20080205906A1

公开(公告)日：2008-08-28

申请号：US11960689

申请日：2007-12-19

申请人： Tomoo Murata

发明人： Tomoo Murata

IPC分类号： H04B10/06

CPC分类号： H03F3/08 ,  H04B10/6931

摘要： When an optical signal that is a wide dynamic range and different in level depending on burst signals is input as in a GPON system, a preamplifier can stably control the gain within a short preamble. The gain changeover of the preamplifier is controlled by the aid of timing information that is extracted from a data signal as data count number, to change over the gain at a high speed and with high precision. A level detector, a preamble recovery, a counter, and a control circuit are disposed within the preamplifier in addition to a TIA main body. In order to suppress the band deterioration or the phase margin reduction which are attributable to the gain changeover, there is provided a bias terminal for conducting a current injection and a current drawing with respect to the signal amplification transistor of the TIA main body.

摘要翻译： 当像GPON系统那样输入根据突发信号的宽动态范围和电平不同的光信号时，前置放大器可以稳定地控制短前导码内的增益。 借助于从数据信号提取的定时信息作为数据计数，来控制前置放大器的增益切换，以高速和高精度切换增益。 电平检测器，前同步码恢复，计数器和控制电路除了TIA主体之外还设置在前置放大器内。 为了抑制归因于增益切换的频带劣化或相位裕度降低，提供了一种用于对TIA主体的信号放大晶体管进行电流注入和电流抽取的偏置端子。

公开(公告)号：US08421512B2

公开(公告)日：2013-04-16

申请号：US13166709

申请日：2011-06-22

申请人： Tomoo Murata ,  Takeo Yamashita

发明人： Tomoo Murata ,  Takeo Yamashita

IPC分类号： H03K3/017

CPC分类号： H03K5/1565

摘要： A duty compensation circuit including a duty detection circuit, a duty adjustment signal generator for generating a control signal from a detected duty, and a duty adjustment circuit, in which the duty detection circuit executes sampling of a clock at sampling timing obtained by causing the clock to be delayed by a variable delay circuit, thereby detecting a duty. Thereby, duty compensation is enabled without preparing a clock higher in operating speed than a clock before compensation.

摘要翻译： 一种占空比补偿电路，包括占空比检测电路，用于从检测到的占空比产生控制信号的占空比调节信号发生器和占空比调整电路，其中占空比检测电路在采样时刻执行采样时钟的采样， 被可变延迟电路延迟，从而检测占空比。 因此，在不准备运行速度比在补偿之前的时钟更高的时钟的情况下，实现占空比补偿。

公开(公告)号：US07962047B2

公开(公告)日：2011-06-14

申请号：US11960689

申请日：2007-12-19

申请人： Tomoo Murata

发明人： Tomoo Murata

IPC分类号： H04B10/00

CPC分类号： H03F3/08 ,  H04B10/6931

摘要： When an optical signal that is a wide dynamic range and different in level depending on burst signals is input as in a GPON system, a preamplifier can stably control the gain within a short preamble. The gain changeover of the preamplifier is controlled by the aid of timing information that is extracted from a data signal as data count number, to change over the gain at a high speed and with high precision. A level detector, a preamble recovery, a counter, and a control circuit are disposed within the preamplifier in addition to a TIA main body. In order to suppress the band deterioration or the phase margin reduction which are attributable to the gain changeover, there is provided a bias terminal for conducting a current injection and a current drawing with respect to the signal amplification transistor of the TIA main body.

摘要翻译： 当像GPON系统那样输入根据突发信号的宽动态范围和电平不同的光信号时，前置放大器可以稳定地控制短前导码内的增益。 借助于从数据信号提取的定时信息作为数据计数，来控制前置放大器的增益切换，以高速和高精度切换增益。 电平检测器，前同步码恢复，计数器和控制电路除了TIA主体之外还设置在前置放大器内。 为了抑制归因于增益切换的频带劣化或相位裕度降低，提供了一种用于对TIA主体的信号放大晶体管进行电流注入和电流抽取的偏置端子。

公开(公告)号：US20100110751A1

公开(公告)日：2010-05-06

申请号：US12603623

申请日：2009-10-22

申请人： Kentaro Miyajima ,  Takeo Yamashita ,  Tomoo Murata

发明人： Kentaro Miyajima ,  Takeo Yamashita ,  Tomoo Murata

IPC分类号： G11C11/00 ,  G11C7/00 ,  G11C8/08 ,  G11C17/18

CPC分类号： G11C7/02 ,  G11C7/20 ,  G11C17/16 ,  G11C17/165 ,  G11C17/18

摘要： In a configuration having a nonvolatile memory and a volatile memory, when storage information of the nonvolatile memory is changed and an abnormal operation occurs due to temporary blackout, α-ray or others, the abnormal operation is recovered to a normal operation regardless of the presence of the detection of the abnormal operation. A reset to be inputted to the nonvolatile memory is collectively transmitted for each 1 bit, each 1 word or each predetermined arbitrary bit, and the collectively transmitted reset serving as one unit is periodically transmitted, so that the abnormal operation is recovered to a normal operation without input signals from outside even if the storage information of the nonvolatile memory is changed due to temporary blackout, α-ray or others.

摘要翻译： 在具有非易失性存储器和易失性存储器的配置中，当非易失性存储器的存储信息改变并且由于暂时中断，α射线等而发生异常操作时，异常操作恢复到正常操作，而不管存在 的异常操作的检测。 对于每1位，每1个字或每个预定的任意位，共同地发送要输入到非易失性存储器的复位，并且周期性地发送作为一个单元的共同发送的复位，使得异常操作恢复到正常操作 即使非易失性存储器的存储信息由于暂时中断，α射线等而改变，也没有来自外部的输入信号。