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公开(公告)号：US06548358B2
公开(公告)日：2003-04-15
申请号：US09769494
申请日：2001-01-26
IPC分类号： H01L21336
CPC分类号： H01L23/62 , H01L23/5256 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor fuse is positioned between conductors for connecting wiring lines. The fuse comprises spacers positioned on adjacent ones of the conductors, and a fuse element positioned between the spacers and connected to the wiring lines. A space between the conductors comprises a first width comprising a smallest possible photolithographic width and the fuse element has a second width smaller than the first width.
摘要翻译： 半导体保险丝位于用于连接布线的导体之间。 保险丝包括位于相邻导体上的间隔物，以及定位在间隔件之间并连接到布线的熔丝元件。 导体之间的空间包括包含尽可能小的光刻宽度的第一宽度，并且熔丝元件具有小于第一宽度的第二宽度。
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公开(公告)号：US06573585B2
公开(公告)日：2003-06-03
申请号：US09769453
申请日：2001-01-26
IPC分类号： H01L2900
CPC分类号： H01L23/62 , H01L23/5256 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor fuse is positioned between conductors for connecting wiring lines. The fuse comprises spacers positioned on adjacent ones of the conductors, and a fuse element positioned between the spacers and connected to the wiring lines. A space between the conductors comprises a first width comprising a smallest possible photolithographic width and the fuse element has a second width smaller than the first width.
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公开(公告)号：US06222244B1
公开(公告)日：2001-04-24
申请号：US09093903
申请日：1998-06-08
IPC分类号： H01L2900
CPC分类号： H01L23/62 , H01L23/5256 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor fuse is positioned between conductors for connecting wiring lines. The fuse comprises spacers positioned on adjacent ones of the conductors, and a fuse element positioned between the spacers and connected to the wiring lines. A space between the conductors comprises a first width comprising a smallest possible photolithographic width and the fuse element has a second width smaller than the first width.
摘要翻译： 半导体保险丝位于用于连接布线的导体之间。 保险丝包括位于相邻导体上的间隔物，以及定位在间隔件之间并连接到布线的熔丝元件。 导体之间的空间包括包含尽可能小的光刻宽度的第一宽度，并且熔丝元件具有小于第一宽度的第二宽度。
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公开(公告)号：US06278171B1
公开(公告)日：2001-08-21
申请号：US09734668
申请日：2000-12-13
IPC分类号： H01L2900
摘要： A method for forming an interconnect wiring structure, such as a fuse structure, comprises forming an opening in an insulating layer using a phase shift mask (the opening having vertical sidewalls sloped sidewalls and horizontal surfaces), depositing a conductive material in the opening and removing the conductive material from the sloped sidewalls and horizontal surfaces, wherein the conductive material remains on the vertical sidewalls as fuse links.
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公开(公告)号：US06190986B1
公开(公告)日：2001-02-20
申请号：US09224768
申请日：1999-01-04
IPC分类号： H01L2122
CPC分类号： H01L23/5258 , H01L2924/0002 , Y10S438/947 , H01L2924/00
摘要： A method for forming an interconnect wiring structure, such as a fuse structure, comprises forming an opening in an insulating layer using a phase shift mask (the opening having vertical sidewalls sloped sidewalls and horizontal surfaces), depositing a conductive material in the opening and removing the conductive material from the sloped sidewalls and horizontal surfaces, wherein the conductive material remains on the vertical sidewalls as fuse links.
摘要翻译： 用于形成诸如熔丝结构的互连布线结构的方法包括使用相移掩模（具有垂直侧壁倾斜的侧壁和水平表面的开口）在绝缘层中形成开口，在开口中沉积导电材料并除去 来自倾斜侧壁和水平表面的导电材料，其中导电材料作为熔丝链保持在垂直侧壁上。
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公开(公告)号：US5966339A
公开(公告)日：1999-10-12
申请号：US88889
申请日：1998-06-02
CPC分类号： G11C29/781 , G11C17/16
摘要： A programmable/reprogrammable fuse arrangement that includes two fuse links provided each with an output port and an exclusive-or gate connected to the output port of each of the two fuses, wherein the fuse arrangement is reprogrammed by successively blowing both of the two fuse links is described. The programmable/reprogrammable fuse arrangement can be extended to a plurality of fuses and cascaded exclusive-ORs such that each fuse link provides one leg of the gate and the previous stage, the second. Thus, for N fuse links and N exclusive-ORs, the fuse arrangement thus formed can be reprogrammed a total of N times by sequentially blowing one fuse link at a time. The arrangement ceases to be reprogrammable once all the fuse links have been blown. The reprogrammable fuse arrangement is of particular importance for semiconductor memories and microprocessors, as for instance, for bringing in-line redundancy units attached to a fuse link.
摘要翻译： 一种可编程/可重新编程的熔丝装置，包括两个熔丝链，每个熔断器具有输出端口和连接到两个保险丝中的每一个的输出端口的异或门，其中熔丝装置通过连续地吹送两个熔丝连接 被描述。 可编程/可重新编程的熔丝布置可以扩展到多个熔丝和级联异或，使得每个熔丝连接提供栅极的一条支脚和前一级，第二级。 因此，对于N个熔丝链路和N个异或，由此形成的熔丝装置可以通过一次顺序吹送一个熔丝链而重新编程N次。 一旦所有的熔断体熔断，该装置就不再可编程了。 可重编程熔丝装置对于半导体存储器和微处理器是特别重要的，例如用于连接到熔丝链路的在线冗余单元。
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7.发明授权Semiconductor structure including a conductive fuse and process for fabrication thereof 失效包括导电熔丝的半导体结构及其制造方法
公开(公告)号：US6037648A
公开(公告)日：2000-03-14
申请号：US105647
申请日：1998-06-26
申请人： Kenneth C. Arndt , Jeffrey P. Gambino , Jack A. Mandelman , Chandrasekhar Narayan , Rainer F. Schnabel , Ronald J. Schutz , Dirk Tobben
发明人： Kenneth C. Arndt , Jeffrey P. Gambino , Jack A. Mandelman , Chandrasekhar Narayan , Rainer F. Schnabel , Ronald J. Schutz , Dirk Tobben
IPC分类号： H01L21/82 , H01L21/768 , H01L23/525 , H01L29/00
CPC分类号： H01L21/76885 , H01L23/5256 , H01L2924/0002
摘要： A semiconductor structure comprising a semiconductor substrate, an electrically conductive level on the substrate and a metal fuse located at the conductive level wherein the fuse comprises a self-aligned dielectric etch stop layer thereon is provided along with processes for its fabrication.
摘要翻译： 包括半导体衬底的半导体结构，衬底上的导电电平和位于导电水平处的金属熔断器，其中熔丝包括其上的自对准电介质蚀刻停止层以及其制造工艺。
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公开(公告)号：US06274440B1
公开(公告)日：2001-08-14
申请号：US09282134
申请日：1999-03-31
申请人： Kenneth C. Arndt , Axel C. Brintzinger , Richard A. Conti , Donna R. Cote , Chandrasekhar Narayan , Ravikumar Ramachandran , Thomas S. Rupp , Senthil K. Srinivasan
发明人： Kenneth C. Arndt , Axel C. Brintzinger , Richard A. Conti , Donna R. Cote , Chandrasekhar Narayan , Ravikumar Ramachandran , Thomas S. Rupp , Senthil K. Srinivasan
IPC分类号： H01L21336
CPC分类号： H01L23/5258 , H01L23/5256 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： A structure and method for making a cavity fuse over a gate conductor stack. The method includes providing a semiconductor substrate having a gate conductor stack over a shallow trench isolation region, forming oxide layers on the substrate about the gate conductor stack, etching electrical contact holes through the oxide layers to the substrate, filling the electrical contact holes with a first conductive material to establish electrical contact with the gate conductor stack, etching a pattern in an uppermost oxide layer of the oxide layers, depositing a conductive layer of a second conductive material over the oxide layers and the electrical contacts, planarizing the conductive layer whereby the conductive material remains only in the pattern, anisotropically etching the oxide layers to form at least one etching hole through the oxide layers to the shallow trench isolation region, and isotropically etching at least a portion of the oxide layers about the etching hole, whereby a cavity is formed beneath at least a portion of the conductive layer pattern, the gate conductor stack comprising a fuse.
摘要翻译： 用于在栅极导体堆叠上形成腔体熔断器的结构和方法。 该方法包括提供在浅沟槽隔离区域上具有栅极导体堆叠的半导体衬底，在栅极导体堆叠周围形成衬底周围的氧化物层，蚀刻通过氧化物层到衬底的电接触孔， 第一导电材料以与栅极导体堆叠建立电接触，蚀刻氧化物层的最上面的氧化物层中的图案，在氧化物层和电触点上沉积第二导电材料的导电层，平坦化导电层，由此 导电材料仅保留在图案中，各向异性地蚀刻氧化物层以形成通过氧化物层到浅沟槽隔离区域的至少一个蚀刻孔，并且在蚀刻孔周围各向同性蚀刻至少一部分氧化层， 形成在导电层图案的至少一部分之下，g 包括保险丝的导体堆叠。
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公开(公告)号：US5939335A
公开(公告)日：1999-08-17
申请号：US3107
申请日：1998-01-06
申请人： Kenneth C. Arndt , Richard A. Conti , David M. Dobuzinsky , Laertis Economikos , Jeffrey P. Gambino , Peter D. Hoh , Chandrasekhar Narayan
发明人： Kenneth C. Arndt , Richard A. Conti , David M. Dobuzinsky , Laertis Economikos , Jeffrey P. Gambino , Peter D. Hoh , Chandrasekhar Narayan
IPC分类号： H01L21/302 , H01L21/3065 , H01L21/3205 , H01L21/3213 , H01L21/768 , H01L21/336
CPC分类号： H01L21/76804 , H01L21/32136 , H01L21/76835 , H01L21/76885
摘要： The stresses commonly induced in the dielectrics of integrated circuits manufactured using metal patterning methods, such as reactive ion etching (RIE) and damascene techniques, can be reduced by rounding the lower corners associated with the features which are formed as part of the integrated circuit (e.g., the interconnects) before applying the outer (i.e., passivation) layer. In connection with the formation of metal lines patterned by a metal RIE process, such corner rounding can be achieved using a two-step metal etching process including a first step which produces a vertical sidewall and a second step which tapers lower portions of the vertical sidewall or which produces a tapered spacer along the lower portions of the vertical sidewall. This results in a rounded bottom corner which improves the step coverage of the overlying dielectric, in turn eliminating the potential for cracks. For metal lines patterned by damascene, such corner rounding can be achieved using a two-step trench etching process including a first step which produces a vertical sidewall, and a second step which produces a tapered sidewall along lower portions of the vertical sidewall.
摘要翻译： 通过使与金属图案化方法（例如反应离子蚀刻（RIE）和镶嵌技术）一起制造的集成电路的电介质中通常感应的应力可以通过将与形成为集成电路的一部分的特征相关联的下角 在施加外部（即钝化）层之前，例如，互连）。 关于通过金属RIE工艺形成的金属线的形成，可以使用包括产生垂直侧壁的第一步骤和使垂直侧壁的下部逐渐变细的第二步骤的两步金属蚀刻工艺来实现这种角圆化 或者沿着垂直侧壁的下部产生锥形间隔物。 这导致圆角的底角，其改善了上覆电介质的台阶覆盖，从而消除了裂纹的可能性。 对于由大马士革图案化的金属线，可以使用包括产生垂直侧壁的第一步骤的两步沟槽蚀刻工艺，以及沿着垂直侧壁的下部产生锥形侧壁的第二步骤来实现这种角落圆化。
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公开(公告)号：US4852504A
公开(公告)日：1989-08-01
申请号：US209703
申请日：1988-06-20
摘要： A waste fuel incineration process and system operates at very high temperatures with excess under fire air for high efficiency combustion of waste as a fuel and for decomposition of any toxic waste. The system is applicable for clean burning volume reduction of waste and for power generation and co-generation of heat. The control elements are constructed and arranged and the control circuit programmed for maintaining the primary combustion temperature at a target temperature selected in the range of approximately 1600.degree.-1800.degree. F. (871.degree.-982.degree. C.), for turning on and increasing under fire air to bring the primary combustion chamber flue gasses up to the target temperature, for maintaining the volume rate of flow of under fire air at 150% to 250% of the stoichiometric requirement for complete combustion at normal load, for reducing and turning off under fire air in a first over-temperature range extending above the target temperature, for turning on and increasing over fire air for diluting and cooling flue gasses in a second over-temperature range extending above the first over-temperature range, and for shutting down the under fire air, over fire air and waste fuel feeding cylinder and piston at a selected absolute over-temperature. A variety of safety features are disclosed including a normally closed dump stack on the secondary tower which automatically opens for natural by pass drafting in the event of power failure or excess temperature in the pollution control device. A live "V" shaped gravel bed and ash ram permits removal of slagged gravel for renewing the surface of the hearth.
摘要翻译： 废燃料焚烧过程和系统在非常高的温度下运行，在火焰空气下过量，以便高效率地燃烧废物作为燃料并分解任何有毒废物。 该系统适用于清洁燃烧体积减少废物和发电和热量共同生成。 控制元件被构造和布置，并且控制电路被编程用于将初级燃烧温度保持在大约1600°-1800°F（871°-982℃）范围内选择的目标温度，用于打开和增加 在燃烧空气下将主燃烧室烟道气体达到目标温度，以保持在空气中的流量的体积速率为正常负载下完全燃烧的化学计量要求的150％至250％，以减少和关闭 在超过目标温度的第一超温范围内的火灾空气中，用于在超过第一过温度范围的第二过温范围内对火焰空气进行打开和增加以稀释和冷却烟道气，并关闭 在火灾空气下，超过空气和废气进料缸和活塞在选定的绝对超温。 公开了各种安全特征，其中包括在二级塔架上的常闭堆放堆叠，其在污染控制装置中的电源故障或过热的情况下通过通过牵伸而自动打开。 一个活的“V”形砾石床和灰ram子可以清除排渣的砾石，以更新炉膛的表面。
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