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    Method for reducing stress in the metallization of an integrated circuit
    1.
    发明授权
    Method for reducing stress in the metallization of an integrated circuit 失效
    降低集成电路金属化应力的方法

    公开(公告)号：US5939335A

    公开(公告)日：1999-08-17

    申请号：US3107

    申请日：1998-01-06

    申请人： Kenneth C. Arndt ,  Richard A. Conti ,  David M. Dobuzinsky ,  Laertis Economikos ,  Jeffrey P. Gambino ,  Peter D. Hoh ,  Chandrasekhar Narayan

    发明人： Kenneth C. Arndt ,  Richard A. Conti ,  David M. Dobuzinsky ,  Laertis Economikos ,  Jeffrey P. Gambino ,  Peter D. Hoh ,  Chandrasekhar Narayan

    IPC分类号： H01L21/302 ,  H01L21/3065 ,  H01L21/3205 ,  H01L21/3213 ,  H01L21/768 ,  H01L21/336

    CPC分类号： H01L21/76804 ,  H01L21/32136 ,  H01L21/76835 ,  H01L21/76885

    摘要： The stresses commonly induced in the dielectrics of integrated circuits manufactured using metal patterning methods, such as reactive ion etching (RIE) and damascene techniques, can be reduced by rounding the lower corners associated with the features which are formed as part of the integrated circuit (e.g., the interconnects) before applying the outer (i.e., passivation) layer. In connection with the formation of metal lines patterned by a metal RIE process, such corner rounding can be achieved using a two-step metal etching process including a first step which produces a vertical sidewall and a second step which tapers lower portions of the vertical sidewall or which produces a tapered spacer along the lower portions of the vertical sidewall. This results in a rounded bottom corner which improves the step coverage of the overlying dielectric, in turn eliminating the potential for cracks. For metal lines patterned by damascene, such corner rounding can be achieved using a two-step trench etching process including a first step which produces a vertical sidewall, and a second step which produces a tapered sidewall along lower portions of the vertical sidewall.

    摘要翻译： 通过使与金属图案化方法（例如反应离子蚀刻（RIE）和镶嵌技术）一起制造的集成电路的电介质中通常感应的应力可以通过将与形成为集成电路的一部分的特征相关联的下角 在施加外部（即钝化）层之前，例如，互连）。 关于通过金属RIE工艺形成的金属线的形成，可以使用包括产生垂直侧壁的第一步骤和使垂直侧壁的下部逐渐变细的第二步骤的两步金属蚀刻工艺来实现这种角圆化 或者沿着垂直侧壁的下部产生锥形间隔物。 这导致圆角的底角，其改善了上覆电介质的台阶覆盖，从而消除了裂纹的可能性。 对于由大马士革图案化的金属线，可以使用包括产生垂直侧壁的第一步骤的两步沟槽蚀刻工艺，以及沿着垂直侧壁的下部产生锥形侧壁的第二步骤来实现这种角落圆化。

    Integrated circuits having reduced stress in metallization
    2.
    发明授权
    Integrated circuits having reduced stress in metallization 失效
    集成电路在金属化中具有降低的应力

    公开(公告)号：US06208008B1

    公开(公告)日：2001-03-27

    申请号：US09260702

    申请日：1999-03-02

    申请人： Kenneth C. Arndt ,  Richard A. Conti ,  David M. Dobuzinsky ,  Laertis Economikos ,  Jeffrey P. Gambino ,  Peter D. Hoh ,  Chandrasekhar Narayan

    发明人： Kenneth C. Arndt ,  Richard A. Conti ,  David M. Dobuzinsky ,  Laertis Economikos ,  Jeffrey P. Gambino ,  Peter D. Hoh ,  Chandrasekhar Narayan

    IPC分类号： H01L2941

    CPC分类号： H01L21/76804 ,  H01L21/32136 ,  H01L21/76835 ,  H01L21/76885

    摘要： The stresses commonly induced in the dielectrics of integrated circuits manufactured using metal patterning methods, such as reactive ion etching (RIE) and damascene techniques, can be reduced by rounding the lower corners associated with the features which are formed as part of the integrated circuit (e.g., the interconnects) before applying the outer (i.e., passivation) layer. In connection with the formation of metal lines patterned by a metal RIE process, such corner rounding can be achieved using a two-step metal etching process including a first step which produces a vertical sidewall and a second step which tapers lower portions of the vertical sidewall or which produces a tapered spacer along the lower portions of the vertical sidewall. This results in a rounded bottom corner which improves the step coverage of the overlying dielectric, in turn eliminating the potential for cracks. For metal lines patterned by damascene, such corner rounding can be achieved using a two-step trench etching process including a first step which produces a vertical sidewall, and a second step which produces a tapered sidewall along lower portions of the vertical sidewall.

    摘要翻译： 通过使与金属图案化方法（例如反应离子蚀刻（RIE）和镶嵌技术）一起制造的集成电路的电介质中通常引起的应力可以通过将与形成为集成电路的一部分的特征相关联的下角 在施加外部（即钝化）层之前，例如，互连）。 关于通过金属RIE工艺形成的金属线的形成，可以使用包括产生垂直侧壁的第一步骤和使垂直侧壁的下部逐渐变细的第二步骤的两步金属蚀刻工艺来实现这种角圆化 或者沿着垂直侧壁的下部产生锥形间隔物。 这导致圆角的底角，其改善了上覆电介质的台阶覆盖，从而消除了裂纹的可能性。 对于由大马士革图案化的金属线，可以使用包括产生垂直侧壁的第一步骤的两步沟槽蚀刻工艺，以及沿着垂直侧壁的下部产生锥形侧壁的第二步骤来实现这种角落圆化。

    Manufacturing of cavity fuses on gate conductor level
    4.
    发明授权
    Manufacturing of cavity fuses on gate conductor level 失效
    在栅极导体级制造腔体保险丝

    公开(公告)号：US06274440B1

    公开(公告)日：2001-08-14

    申请号：US09282134

    申请日：1999-03-31

    申请人： Kenneth C. Arndt ,  Axel C. Brintzinger ,  Richard A. Conti ,  Donna R. Cote ,  Chandrasekhar Narayan ,  Ravikumar Ramachandran ,  Thomas S. Rupp ,  Senthil K. Srinivasan

    发明人： Kenneth C. Arndt ,  Axel C. Brintzinger ,  Richard A. Conti ,  Donna R. Cote ,  Chandrasekhar Narayan ,  Ravikumar Ramachandran ,  Thomas S. Rupp ,  Senthil K. Srinivasan

    IPC分类号： H01L21336

    CPC分类号： H01L23/5258 ,  H01L23/5256 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

    摘要： A structure and method for making a cavity fuse over a gate conductor stack. The method includes providing a semiconductor substrate having a gate conductor stack over a shallow trench isolation region, forming oxide layers on the substrate about the gate conductor stack, etching electrical contact holes through the oxide layers to the substrate, filling the electrical contact holes with a first conductive material to establish electrical contact with the gate conductor stack, etching a pattern in an uppermost oxide layer of the oxide layers, depositing a conductive layer of a second conductive material over the oxide layers and the electrical contacts, planarizing the conductive layer whereby the conductive material remains only in the pattern, anisotropically etching the oxide layers to form at least one etching hole through the oxide layers to the shallow trench isolation region, and isotropically etching at least a portion of the oxide layers about the etching hole, whereby a cavity is formed beneath at least a portion of the conductive layer pattern, the gate conductor stack comprising a fuse.

    摘要翻译： 用于在栅极导体堆叠上形成腔体熔断器的结构和方法。 该方法包括提供在浅沟槽隔离区域上具有栅极导体堆叠的半导体衬底，在栅极导体堆叠周围形成衬底周围的氧化物层，蚀刻通过氧化物层到衬底的电接触孔， 第一导电材料以与栅极导体堆叠建立电接触，蚀刻氧化物层的最上面的氧化物层中的图案，在氧化物层和电触点上沉积第二导电材料的导电层，平坦化导电层，由此 导电材料仅保留在图案中，各向异性地蚀刻氧化物层以形成通过氧化物层到浅沟槽隔离区域的至少一个蚀刻孔，并且在蚀刻孔周围各向同性蚀刻至少一部分氧化层， 形成在导电层图案的至少一部分之下，g 包括保险丝的导体堆叠。

    Conductor-insulator-conductor structure
    5.
    发明授权
    Conductor-insulator-conductor structure 失效
    导体 - 绝缘体导体结构

    公开(公告)号：US6081021A

    公开(公告)日：2000-06-27

    申请号：US7889

    申请日：1998-01-15

    申请人： Jeffrey P. Gambino ,  Chandrasekhar Narayan ,  Toshiaki Kirihata

    发明人： Jeffrey P. Gambino ,  Chandrasekhar Narayan ,  Toshiaki Kirihata

    IPC分类号： H01L21/02 ,  H01L21/316 ,  H01L21/318 ,  H01L21/768 ,  H01L29/00

    CPC分类号： H01L28/40 ,  H01L21/76807 ,  H01L21/76831 ,  H01L21/76838 ,  H01L21/76885 ,  H01L23/5252 ,  H01L28/60 ,  H01L21/31612 ,  H01L21/3185 ,  H01L2924/0002

    摘要： An integrated circuit device including a conductor-insulator-conductor structure and a method of manufacturing the structure simultaneously while forming a dual damascene via. A first interconnect layer is formed upon a first interlevel dielectric. Openings extend through a second interlevel dielectric to the first interconnect layer. An insulator is deposited in the openings. A trench is then etched into the upper portion of the openings that will become vias while simultaneously removing the insulator from the bottom of the openings that will become vias. A conductor is then deposited in the openings and in the trenches and chemical-mechanical polishing (CMP) is used to pattern the conductor. A third interlevel dielectric is then deposited, openings are formed extending to the conductors, and third interconnect layer conductors are deposited and patterned.

    摘要翻译： 一种包括导体 - 绝缘体 - 导体结构的集成电路器件以及同时形成双重镶嵌通孔同时制造该结构的方法。 第一互连层形成在第一层间电介质上。 开口延伸穿过第二层间介质到第一互连层。 绝缘体沉积在开口中。 然后将沟槽蚀刻到将成为通孔的开口的上部中，同时从将成为通孔的开口的底部移除绝缘体。 然后将导体沉积在开口中并在沟槽中，并使用化学机械抛光（CMP）来对导体进行图案化。 然后沉积第三层间电介质，形成延伸到导体的开口，并且沉积和图案化第三互连层导体。

    Mixed fuse technologies
    9.
    发明授权
    Mixed fuse technologies 失效
    混合保险丝技术

    公开(公告)号：US06288436B1

    公开(公告)日：2001-09-11

    申请号：US09361960

    申请日：1999-07-27

    申请人： Chandrasekhar Narayan ,  Kenneth Arndt ,  Toshiaki Kirihata ,  David Lachtrupp ,  Axel Brintzinger ,  Gabriel Daniel

    发明人： Chandrasekhar Narayan ,  Kenneth Arndt ,  Toshiaki Kirihata ,  David Lachtrupp ,  Axel Brintzinger ,  Gabriel Daniel

    IPC分类号： H01L2900

    CPC分类号： H01L22/22 ,  H01L23/5256 ,  H01L23/5258 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A plurality of fuses of different types, each type of fuse serving a specific purpose are positioned on a semiconductor integrated circuit wafer, wherein activating one type of fuse does not incapacitate fuses of a different type. Fuses of the first type, e.g., laser activated fuses, are primarily used for repairing defects at the wafer level, whereas fuses of the second type, e.g., electrically activated fuses, are used for repairing defects found after mounting the IC chips on a module and stressing the module at burn-in test. Defects at the module level typically are single cell failures which are cured by the electrically programmed fuses to activate module level redundancies.

    摘要翻译： 多种不同类型的保险丝，每种类型的用于特定用途的保险丝都位于半导体集成电路晶片上，其中激活一种类型的保险丝不会使不同类型的保险丝失效。 第一种类型的保险丝，例如激光激活的保险丝，主要用于修复晶圆级的缺陷，而第二种类型的保险丝，例如电激活保险丝，用于修复将IC芯片安装在模块上所发现的缺陷 并在老化测试中强调模块。 模块级别的缺陷通常是单电池故障，它们由电气编程的保险丝固化，以激活模块级冗余。

    Defect management engine for semiconductor memories and memory systems
    10.
    发明授权
    Defect management engine for semiconductor memories and memory systems 有权
    半导体存储器和存储器系统的缺陷管理引擎

    公开(公告)号：US6141267A

    公开(公告)日：2000-10-31

    申请号：US243645

    申请日：1999-02-03

    申请人： Toshiaki Kirihata ,  Louis Lu-Chen Hsu ,  Chandrasekhar Narayan

    发明人： Toshiaki Kirihata ,  Louis Lu-Chen Hsu ,  Chandrasekhar Narayan

    IPC分类号： G11C5/02 ,  G11C8/06 ,  G11C11/00 ,  G11C29/00 ,  G11C7/00

    CPC分类号： G11C29/808 ,  G11C11/005 ,  G11C29/846 ,  G11C5/02 ,  G11C8/06

    摘要： A defect management engine (DME) for memories integrates a plurality of redundancy data cells and a plurality of redundancy address cells in the same array. The redundancy data cells are used for replacing defective cells in the memories. The redundancy address cells store the addresses of the defective cells. The memories are preferably sub-divided into a plurality of domains. A plurality of defective cells in each domain are supported by a plurality of repair units, each consisting of one or more redundancy data bits and redundancy address bits in the DME. When one or more data bits are read from a domain in the memory, the corresponding wordline in the DME simultaneously activates a plurality of repair units coupling to the wordline (self-contained domain selection). The redundancy data bits and the redundancy address bits are also read from the redundancy data cells and redundancy address cells, respectively. The DME logic detects whether or not the redundancy address bits match or do not match the address inputs of each repair unit (self contained redundancy match detection). This couples either redundancy data bits from the DME (i.e., a matching condition) or the data bits from the domain in the memories (i.e., a no match condition) to the corresponding DQ (self-contained redundancy replacement). The DME enables an integrated redundancy means (self-contained domain selection, self-contained redundancy match detection, and self-contained redundancy replacement). Single bit replacement, multi-bit replacement, line replacement, and variable bit size replacement are discussed. Finally, an extension of the DME concept to a memory system is also discussed.

    摘要翻译： 用于存储器的缺陷管理引擎（DME）将多个冗余数据单元和多个冗余地址单元集成在相同的阵列中。 冗余数据单元用于替换存储器中的有缺陷的单元。 冗余地址单元存储有缺陷单元的地址。 存储器优选地被细分为多个域。 每个域中的多个缺陷单元由多个修复单元支持，每个修复单元由DME中的一个或多个冗余数据位和冗余地址位组成。 当从存储器中的域读取一个或多个数据位时，DME中的相应字线同时激活耦合到字线（自包含域选择）的多个修复单元。 冗余数据位和冗余地址位也分别从冗余数据单元和冗余地址单元读取。 DME逻辑检测冗余地址位是否匹配或不匹配每个修复单元的地址输入（自包含冗余匹配检测）。 这将来自DME的冗余数据位（即，匹配条件）或来自存储器中的域的数据位（即，不匹配条件）耦合到相应的DQ（独立冗余替换）。 DME可实现集成的冗余手段（自包含域选择，独立冗余匹配检测和自包含冗余替换）。 讨论了单位替换，多位替换，线替换和可变位大小替换。 最后还讨论了将DME概念扩展到内存系统。