STM-1 to STM-64 SDH/SONET framer with data multiplexing from a series of configurable I/O ports
    2.
    发明授权
    STM-1 to STM-64 SDH/SONET framer with data multiplexing from a series of configurable I/O ports 有权
    STM-1至STM-64 SDH / SONET成帧器,具有来自一系列可配置I / O端口的数据复用功能

    公开(公告)号:US08130792B2

    公开(公告)日:2012-03-06

    申请号:US11467848

    申请日:2006-08-28

    IPC分类号: H04J3/00 H04J3/02

    摘要: The present invention relates to a device for combining at least two data signals having an input data rate into a single data stream having an output data rate being higher than the input data rate for transmission on a shared medium or vice versa, particularly, to a single SDH/SONET framer capable of handling a large range of SDH/SONET frames from STM-i to STM-j with an aggregated total capacity corresponding to an STM-j frame where i and j are integers in the range from 1 to 64 or higher according to the STM-N definition of the SDH/SONET standards. More over, the present invention can also be extended to work with STS-1 as lowest range. STS-1 exists in SONET only not SDH and corresponds to a data rate of 51.5 Mb/s a third of the 156 Mb/s of STM-1. The device according to the present invention comprises at least two ports for receiving and/or sending said at least two data signals, a port scanning unit for extracting data from the data signals received by said ports and/or synthesizing data to be transmitted via the ports, respectively, whereby said port scanning unit is configured to extract data from ports providing data streams having at least two different input data rates and/or to synthesize data to be transmitted via the ports taking data streams having at least two different data rates.

    摘要翻译: 本发明涉及一种用于将具有输入数据速率的至少两个数据信号组合成具有高于用于在共享介质上传输的输入数据速率的输出数据速率的单个数据流的装置,反之亦然,特别涉及一种 单个SDH / SONET成帧器能够处理从STM-i到STM-j的大范围的SDH / SONET帧,具有对应于STM-j帧的聚合总容量,其中i和j是从1到64的整数或 根据SDH / SONET标准的STM-N定义更高。 此外,本发明也可以扩展到使用STS-1作为最低范围。 STS-1仅存在于SONET中,不存在SDH,对应于156Mb / s的STM-1的1/3的数据速率为51.5Mb / s。 根据本发明的装置包括用于接收和/或发送所述至少两个数据信号的至少两个端口,用于从由所述端口接收的数据信号中提取数据和/或合成要通过所述端口发送的数据的端口扫描单元 其中所述端口扫描单元被配置为从提供具有至少两个不同输入数据速率的数据流的端口提取数据和/或合成要通过端口发送的数据,该数据流具有至少两个不同数据速率的数据流。

    STM-1 to STM-64 SDH/SONET framer with data multiplexing from a series of configurable I/O ports
    3.
    发明授权
    STM-1 to STM-64 SDH/SONET framer with data multiplexing from a series of configurable I/O ports 失效
    STM-1至STM-64 SDH / SONET成帧器,具有来自一系列可配置I / O端口的数据复用功能

    公开(公告)号:US07161961B2

    公开(公告)日:2007-01-09

    申请号:US09880450

    申请日:2001-06-13

    IPC分类号: H04J3/00 H04J3/02 H04L12/56

    摘要: The present invention relates to a device for combining at least two data signals having an input data rate into a single data stream having an output data rate being higher than the input data rate for transmission on a shared medium or vice versa, particularly, to a single SDH/SONET framer capable of handling a large range of SDH/SONET frames from STM-i to STM-j with an aggregated total capacity corresponding to an STM-j frame where i and j are integers in the range from 1 to 64 or higher according to the STM-N definition of the SDH/SONET standards. More over, the present invention can also be extended to work with STS-1 as lowest range. STS-1 exists in SONET only not SDH and corresponds to a data rate of 51.5 Mb/s a third of the 156 Mb/s of STM-1. The device according to the present invention comprises at least two ports for receiving and/or sending said at least two data signals, a port scanning unit for extracting data from the data signals received by said ports and/or synthesizing data to be transmitted via the ports, respectively, whereby said port scanning unit is configured to extract data from ports providing data streams having at least two different input data rates and/or to synthesize data to be transmitted via the ports taking data streams having at least two different data rates.

    摘要翻译: 本发明涉及一种用于将具有输入数据速率的至少两个数据信号组合成具有高于用于在共享介质上传输的输入数据速率的输出数据速率的单个数据流的装置,反之亦然,特别涉及一种 单个SDH / SONET成帧器能够处理从STM-i到STM-j的大范围的SDH / SONET帧,具有对应于STM-j帧的聚合总容量,其中i和j是从1到64的整数或 根据SDH / SONET标准的STM-N定义更高。 此外,本发明也可以扩展到使用STS-1作为最低范围。 STS-1仅存在于SONET中,不存在SDH,对应于156Mb / s的STM-1的1/3的数据速率为51.5Mb / s。 根据本发明的装置包括用于接收和/或发送所述至少两个数据信号的至少两个端口,用于从由所述端口接收的数据信号中提取数据和/或合成要通过所述端口发送的数据的端口扫描单元 其中所述端口扫描单元被配置为从提供具有至少两个不同输入数据速率的数据流的端口提取数据和/或合成要通过端口发送的数据,该数据流具有至少两个不同数据速率的数据流。

    Architecture and apparatus for implementing 100 Mbps and GBPS Ethernet adapters
    5.
    发明授权
    Architecture and apparatus for implementing 100 Mbps and GBPS Ethernet adapters 失效
    用于实现100 Mbps和GBPS以太网适配器的架构和设备

    公开(公告)号:US06393457B1

    公开(公告)日:2002-05-21

    申请号:US09114761

    申请日:1998-07-13

    IPC分类号: H04J314

    摘要: An architecture and NIC (Network Interface Card) for coupling Data Processing Equipment to a communications network includes a host memory having a High Priority Queue storing control information and data, a Low Priority Queue storing control information and data. Control registers, in the NIC, store addresses identifying the location of said Queues and a block size register, in the NIC, stores a value representing the size of data blocks to be transferred from the host memory to the NIC. A controller transfers allowable block size data from the host memory to buffers on said NIC.

    摘要翻译: 用于将数据处理设备耦合到通信网络的架构和NIC(网络接口卡)包括具有存储控制信息和数据的高优先级队列的主机存储器,存储控制信息和数据的低优先级队列。 NIC中的控制寄存器存储标识所述队列的位置的地址和块大小寄存器,其在NIC中存储表示要从主机存储器传送到NIC的数据块的大小的值。 控制器将允许的块大小数据从主机存储器传送到所述NIC上的缓冲器。

    Architecture and apparatus for implementing 100 MBPS and GBPS ethernet address
    6.
    发明授权
    Architecture and apparatus for implementing 100 MBPS and GBPS ethernet address 有权
    实现100 MBPS和GBPS以太网地址的架构和设备

    公开(公告)号:US06549960B1

    公开(公告)日:2003-04-15

    申请号:US09714643

    申请日:2000-11-16

    IPC分类号: G06F1300

    摘要: An architecture and NIC (Network Interface Card) for coupling Data Processing Equipment to a communications network includes a host memory having a High Priority Queue storing control information and data, a Low Priority Queue storing control information and data. Control registers, in the NIC, store addresses identifying the location of said Queues and a block size register, in the NIC, stores a value representing the size of data blocks to be transferred from the host memory to the NIC. A controller transfers allowable block size data from the host memory to buffers on said NIC.

    摘要翻译: 用于将数据处理设备耦合到通信网络的架构和NIC(网络接口卡)包括具有存储控制信息和数据的高优先级队列的主机存储器,存储控制信息和数据的低优先级队列。 NIC中的控制寄存器存储标识所述队列的位置的地址和块大小寄存器,其在NIC中存储表示要从主机存储器传送到NIC的数据块的大小的值。 控制器将允许的块大小数据从主机存储器传送到所述NIC上的缓冲器。

    Architecture for a multi-port adapter with a single media access control (MAC)
    7.
    发明授权
    Architecture for a multi-port adapter with a single media access control (MAC) 失效
    具有单媒体访问控制(MAC)的多端口适配器的体系结构

    公开(公告)号:US06373848B1

    公开(公告)日:2002-04-16

    申请号:US09123899

    申请日:1998-07-28

    IPC分类号: H04L1256

    摘要: A multi-port adapter having a single MAC chip has reduced logic circuits for transferring data between a host system and a TDM communication system. The MAC chip includes a transmit MAC and a receive MAC, each coupled at one end to a port multiplexer through an interface and at the other end to respective storage registers. The port multiplexer is coupled to the Physical Layer of each port. Transmit and receive state registers track the state of each port in the transfer of data in the transmit and receive directions. The storage registers are coupled through a host bus interface to a host bus and to the host system. Control logic is coupled to the storage register to control the transfer of data between the system and the storage registers. A port selector coupled between the multiplexer and the transmit and receive state registers selects ports for transfer of data in succession. On each chip clock cycle, the port selector selects a state machine register to determine the state of the MACs for processing the data and a section of the FIFO's to write or read data for the selected port. At the end of the cycle, the state registers are set and stay set until selected again. The process repeats for each port in a cyclic manner. Once data is accumulated in the receive storage register, control logic reads the data of the host bus. Once space is available in the transmit storage register, the control logic writes data from the host system to the transmit storage register.

    摘要翻译: 具有单个MAC芯片的多端口适配器具有用于在主机系统和TDM通信系统之间传送数据的减少的逻辑电路。 MAC芯片包括发送MAC和接收MAC,每个MAC在一端通过接口耦合到端口多路复用器,另一端通过相应的存储寄存器耦合。 端口复用器耦合到每个端口的物理层。 发送和接收状态寄存器跟踪发送和接收方向中数据传输中每个端口的状态。 存储寄存器通过主机总线接口耦合到主机总线和主机系统。 控制逻辑耦合到存储寄存器以控制系统和存储寄存器之间的数据传输。 耦合在多路复用器和发送和接收状态寄存器之间的端口选择器选择用于连续传输数据的端口。 在每个芯片时钟周期中,端口选择器选择一个状态机寄存器来确定用于处理数据的MAC的状态以及FIFO的一部分来写入或读取所选端口的数据。 在循环结束时,状态寄存器被设置并保持置位,直到再次选择。 该过程以循环方式重复每个端口。 一旦数据在接收存储寄存器中累积,控制逻辑读取主机总线的数据。 一旦发送存储寄存器中有空间,控制逻辑将数据从主机系统写入发送存储寄存器。

    Method and system for fast ethernet serial port multiplexing to reduce I/O pin count
    8.
    发明授权
    Method and system for fast ethernet serial port multiplexing to reduce I/O pin count 失效
    用于快速以太网串口复用的方法和系统,以减少I / O引脚数

    公开(公告)号:US06980563B2

    公开(公告)日:2005-12-27

    申请号:US09834591

    申请日:2001-04-13

    IPC分类号: H04L12/56 H04J3/16

    CPC分类号: H04L49/351

    摘要: A system and method of reducing the input and output pins used to interface a fast serial port Ethernet processing system using multiplexing. Using the system of the present invention, four pins can allow a plurality of Ethernet communication paths to be connected to a single processor on a substrate. These four connections include a clocking input as well as a strobe signal which coordinates the multiplexing and identifies the time period for a predetermined source. The physical layer and the processor are each provided with a multiplexor which is controlled by the strobe to select the network to be coupled at any given time. The multiplexor includes a counter which is incremented by the clocking input and reset by the strobe signal.

    摘要翻译: 一种减少输入和输出引脚的系统和方法,用于使用多路复用来连接快速串行端口以太网处理系统。 使用本发明的系统,四个引脚可以允许多个以太网通信路径连接到基板上的单个处理器。 这四个连接包括一个时钟输入以及一个选通信号,该信号协调多路复用并识别一个预定的源的时间段。 物理层和处理器均设置有多路复用器,该复用器由选通器控制,以选择要在任何给定时间耦合的网络。 多路复用器包括一个由时钟输入递增并由选通信号复位的计数器。

    Phantom buffer for interfacing between buses of differing speeds
    9.
    发明授权
    Phantom buffer for interfacing between buses of differing speeds 失效
    用于在不同速度的总线之间连接的幻影缓冲器

    公开(公告)号:US06363076B1

    公开(公告)日:2002-03-26

    申请号:US09014334

    申请日:1998-01-27

    IPC分类号: H04L1228

    CPC分类号: G06F13/4059

    摘要: Methods, systems or apparatus and computer program products are provided that interface between two data buses operating at different speeds. Such interfaces utilize a buffer which has an apparent size larger than the physical size of the buffer to receive blocks of data which are larger than the size of the buffer. The apparent size of the buffer is created by simultaneously writing data to and reading data from the buffer such that the same storage locations may be used more than once to hold the data. The present invention may be utilized for receiving data from either the high speed or the lower speed bus.

    摘要翻译: 提供了以不同速度操作的两条数据总线之间进行接口的方法,系统或装置和计算机程序产品。 这样的接口使用具有大于缓冲器的物理大小的表观大小的缓冲器来接收大于缓冲器大小的数据块。 通过同时将数据写入缓冲器和从缓冲器读取数据来创建缓冲器的外观尺寸,使得可以多次使用相同的存储位置来保存数据。 本发明可以用于从高速或低速总线接收数据。

    Dual two byte process for fast wake-up-on LAN frame detection
    10.
    发明授权
    Dual two byte process for fast wake-up-on LAN frame detection 失效
    双双字节进程,用于快速唤醒LAN帧检测

    公开(公告)号:US06339792B1

    公开(公告)日:2002-01-15

    申请号:US09032428

    申请日:1998-02-27

    IPC分类号: G06F1516

    摘要: A detector and method for detecting Wakeup-On-LAN (WOL) frames in which the Wakeup field can start on a two byte word boundary (even) or in the middle of the two byte word (odd). The orientation (even/odd) of the WOL and destination address (DA) fields are determined and a first or second two byte process, depending on the orientation, is selected to analyze the frame to determine if it is valid.

    摘要翻译: 一种用于检测Wake-On-LAN(WOL)帧的检测器和方法,其中Wakeup字段可以在两字节字边界(偶数)或两字节字(奇数)的中间开始。 确定WOL和目标地址(DA)字段的取向(偶数/奇数),并且根据方向选择第一或第二两个字节的进程来分析帧以确定其是否有效。