摘要:
A network processor useful in network switch apparatus and methods of operating such a processor in which data flow handling and flexibility is enhanced by the cooperation of a plurality of interface processors formed on a semiconductor substrate. The interface processors provide data paths for inbound and outbound data flow and operate under the control of instructions stored in an instruction store formed on the semiconductor substrate.
摘要:
The present invention relates to a device for combining at least two data signals having an input data rate into a single data stream having an output data rate being higher than the input data rate for transmission on a shared medium or vice versa, particularly, to a single SDH/SONET framer capable of handling a large range of SDH/SONET frames from STM-i to STM-j with an aggregated total capacity corresponding to an STM-j frame where i and j are integers in the range from 1 to 64 or higher according to the STM-N definition of the SDH/SONET standards. More over, the present invention can also be extended to work with STS-1 as lowest range. STS-1 exists in SONET only not SDH and corresponds to a data rate of 51.5 Mb/s a third of the 156 Mb/s of STM-1. The device according to the present invention comprises at least two ports for receiving and/or sending said at least two data signals, a port scanning unit for extracting data from the data signals received by said ports and/or synthesizing data to be transmitted via the ports, respectively, whereby said port scanning unit is configured to extract data from ports providing data streams having at least two different input data rates and/or to synthesize data to be transmitted via the ports taking data streams having at least two different data rates.
摘要:
The present invention relates to a device for combining at least two data signals having an input data rate into a single data stream having an output data rate being higher than the input data rate for transmission on a shared medium or vice versa, particularly, to a single SDH/SONET framer capable of handling a large range of SDH/SONET frames from STM-i to STM-j with an aggregated total capacity corresponding to an STM-j frame where i and j are integers in the range from 1 to 64 or higher according to the STM-N definition of the SDH/SONET standards. More over, the present invention can also be extended to work with STS-1 as lowest range. STS-1 exists in SONET only not SDH and corresponds to a data rate of 51.5 Mb/s a third of the 156 Mb/s of STM-1. The device according to the present invention comprises at least two ports for receiving and/or sending said at least two data signals, a port scanning unit for extracting data from the data signals received by said ports and/or synthesizing data to be transmitted via the ports, respectively, whereby said port scanning unit is configured to extract data from ports providing data streams having at least two different input data rates and/or to synthesize data to be transmitted via the ports taking data streams having at least two different data rates.
摘要:
Stations in a communications network are awakened by matching a pattern received from the communications network with patterns in the stations. When a match occurs, the stations are awakened. The patterns are arranged contiguously on word boundaries. A nibble (4 bits) in a mask word identifies the part of the pattern word to be used in the comparison.
摘要:
An architecture and NIC (Network Interface Card) for coupling Data Processing Equipment to a communications network includes a host memory having a High Priority Queue storing control information and data, a Low Priority Queue storing control information and data. Control registers, in the NIC, store addresses identifying the location of said Queues and a block size register, in the NIC, stores a value representing the size of data blocks to be transferred from the host memory to the NIC. A controller transfers allowable block size data from the host memory to buffers on said NIC.
摘要:
An architecture and NIC (Network Interface Card) for coupling Data Processing Equipment to a communications network includes a host memory having a High Priority Queue storing control information and data, a Low Priority Queue storing control information and data. Control registers, in the NIC, store addresses identifying the location of said Queues and a block size register, in the NIC, stores a value representing the size of data blocks to be transferred from the host memory to the NIC. A controller transfers allowable block size data from the host memory to buffers on said NIC.
摘要:
A multi-port adapter having a single MAC chip has reduced logic circuits for transferring data between a host system and a TDM communication system. The MAC chip includes a transmit MAC and a receive MAC, each coupled at one end to a port multiplexer through an interface and at the other end to respective storage registers. The port multiplexer is coupled to the Physical Layer of each port. Transmit and receive state registers track the state of each port in the transfer of data in the transmit and receive directions. The storage registers are coupled through a host bus interface to a host bus and to the host system. Control logic is coupled to the storage register to control the transfer of data between the system and the storage registers. A port selector coupled between the multiplexer and the transmit and receive state registers selects ports for transfer of data in succession. On each chip clock cycle, the port selector selects a state machine register to determine the state of the MACs for processing the data and a section of the FIFO's to write or read data for the selected port. At the end of the cycle, the state registers are set and stay set until selected again. The process repeats for each port in a cyclic manner. Once data is accumulated in the receive storage register, control logic reads the data of the host bus. Once space is available in the transmit storage register, the control logic writes data from the host system to the transmit storage register.
摘要:
A system and method of reducing the input and output pins used to interface a fast serial port Ethernet processing system using multiplexing. Using the system of the present invention, four pins can allow a plurality of Ethernet communication paths to be connected to a single processor on a substrate. These four connections include a clocking input as well as a strobe signal which coordinates the multiplexing and identifies the time period for a predetermined source. The physical layer and the processor are each provided with a multiplexor which is controlled by the strobe to select the network to be coupled at any given time. The multiplexor includes a counter which is incremented by the clocking input and reset by the strobe signal.
摘要:
Methods, systems or apparatus and computer program products are provided that interface between two data buses operating at different speeds. Such interfaces utilize a buffer which has an apparent size larger than the physical size of the buffer to receive blocks of data which are larger than the size of the buffer. The apparent size of the buffer is created by simultaneously writing data to and reading data from the buffer such that the same storage locations may be used more than once to hold the data. The present invention may be utilized for receiving data from either the high speed or the lower speed bus.
摘要:
A detector and method for detecting Wakeup-On-LAN (WOL) frames in which the Wakeup field can start on a two byte word boundary (even) or in the middle of the two byte word (odd). The orientation (even/odd) of the WOL and destination address (DA) fields are determined and a first or second two byte process, depending on the orientation, is selected to analyze the frame to determine if it is valid.