公开(公告)号：US20100327366A1

公开(公告)日：2010-12-30

申请号：US12819662

申请日：2010-06-21

申请人： Kenzo MANABE ,  Toshihiro IIZUKA ,  Daisuke IKENO

发明人： Kenzo MANABE ,  Toshihiro IIZUKA ,  Daisuke IKENO

IPC分类号： H01L27/092

CPC分类号： H01L21/823842

摘要： A first adjusting metal, capable of varying the threshold voltage of a first-conductivity-type transistor of a complementary transistor, is added to the first-conductivity-type transistor and a second-conductivity-type transistor at the same time, and a diffusion suppressive element, capable of suppressing diffusion of the first adjusting metal, is added from above a metal gate electrode of the second-conductivity-type transistor.

摘要翻译： 能够改变互补晶体管的第一导电型晶体管的阈值电压的第一调整金属同时被添加到第一导电型晶体管和第二导电型晶体管，并且扩散 从第二导电型晶体管的金属栅电极的上方添加能够抑制第一调整金属的扩散的抑制元件。

公开(公告)号：US20130280872A1

公开(公告)日：2013-10-24

申请号：US13914956

申请日：2013-06-11

申请人： Kenzo MANABE

发明人： Kenzo MANABE

IPC分类号： H01L21/8238

CPC分类号： H01L21/823835 ,  H01L21/28185 ,  H01L21/823857 ,  H01L27/092 ,  H01L29/4966 ,  H01L29/51 ,  H01L29/513 ,  H01L29/517 ,  H01L29/665 ,  H01L29/7833

摘要： A semiconductor device has a substrate; and an N-channel MIS transistor and a P-channel MIS transistor provided on the same substrate; each of the N-channel MIS transistor and the P-channel MIS transistor having a Hf-containing, high-k gate insulating film, and a gate electrode provided over the high-k gate insulating film, the N-channel MIS transistor having a silicon oxide film or a silicon oxynitride film, which contains a first work function adjusting element, provided between the substrate and the high-k gate insulating film, and, the P-channel MIS transistor having a silicon oxide film or a silicon oxynitride film, which contains the first work function adjusting element same as that contained in the N-channel MIS transistor, provided between the high-k gate insulating film and the gate electrode.

摘要翻译： 半导体器件具有基板; 以及设置在同一衬底上的N沟道MIS晶体管和P沟道MIS晶体管; N沟道MIS晶体管和P沟道MIS晶体管中的每一个具有包含Hf的高k栅极绝缘膜和设置在高k栅极绝缘膜上的栅电极，N沟道MIS晶体管具有 含有设置在基板和高k栅极绝缘膜之间的第一功函数调节元件的氧化硅膜或氧氮化硅膜，以及具有氧化硅膜或氮氧化硅膜的P沟道MIS晶体管， 其包括设置在高k栅极绝缘膜和栅电极之间的与N沟道MIS晶体管相同的第一功函数调节元件。

公开(公告)号：US20120193760A1

公开(公告)日：2012-08-02

申请号：US13358133

申请日：2012-01-25

申请人： Kenzo MANABE ,  Naoya INOUE ,  Kenichiro HIJIOKA ,  Yoshihiro HAYASHI

发明人： Kenzo MANABE ,  Naoya INOUE ,  Kenichiro HIJIOKA ,  Yoshihiro HAYASHI

IPC分类号： H01L29/02 ,  H01L21/02

CPC分类号： H01L27/1085 ,  H01L21/768 ,  H01L23/5223 ,  H01L23/53238 ,  H01L23/5329 ,  H01L23/53295 ,  H01L27/10814 ,  H01L27/10852 ,  H01L27/10885 ,  H01L27/10894 ,  H01L28/91 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device includes: a multilayer wiring layer located over a substrate and in which multiple wiring layers configured by a wiring and an insulating layer are stacked; a memory circuit which is formed in a memory circuit region in the substrate and has a capacitance element embedded in a concave part located in the multilayer wiring layer; a logic circuit which is formed in a logic circuit region in the substrate; an upper part coupling wiring which is stacked over the capacitance element configured by a lower part electrode, a capacitor insulating film and an upper part electrode; and a cap layer which is formed on the upper surface of the wiring configuring the logic circuit. The upper surface of the upper part coupling wiring and the upper surface of the cap film are provided on the same plane.

摘要翻译： 一种半导体器件，包括：多层布线层，位于基板的上方，其中堆叠由布线和绝缘层构成的多个布线层; 存储电路，其形成在所述基板的存储电路区域中，并且具有嵌入在位于所述多层布线层中的凹部的电容元件; 形成在基板的逻辑电路区域中的逻辑电路; 层叠在由下部电极，电容绝缘膜和上部电极构成的电容元件上的上部耦合布线; 以及形成在构成逻辑电路的布线的上表面上的盖层。 上部连接线的上表面和盖膜的上表面设置在同一平面上。

公开(公告)号：US20120025321A1

公开(公告)日：2012-02-02

申请号：US13195396

申请日：2011-08-01

申请人： Kenzo MANABE

发明人： Kenzo MANABE

IPC分类号： H01L27/092 ,  H01L21/28

CPC分类号： H01L21/823835 ,  H01L21/28185 ,  H01L21/823857 ,  H01L27/092 ,  H01L29/4966 ,  H01L29/51 ,  H01L29/513 ,  H01L29/517 ,  H01L29/665 ,  H01L29/7833

摘要： A semiconductor device has a substrate; and an N-channel MIS transistor and a P-channel MIS transistor provided on the same substrate; each of the N-channel MIS transistor and the P-channel MIS transistor having a Hf-containing, high-k gate insulating film, and a gate electrode provided over the high-k gate insulating film, the N-channel MIS transistor having a silicon oxide film or a silicon oxynitride film, which contains a first work function adjusting element, provided between the substrate and the high-k gate insulating film, and, the P-channel MIS transistor having a silicon oxide film or a silicon oxynitride film, which contains the first work function adjusting element same as that contained in the N-channel MIS transistor, provided between the high-k gate insulating film and the gate electrode.

摘要翻译： 半导体器件具有基板; 以及设置在同一衬底上的N沟道MIS晶体管和P沟道MIS晶体管; N沟道MIS晶体管和P沟道MIS晶体管中的每一个具有包含Hf的高k栅极绝缘膜和设置在高k栅极绝缘膜上的栅电极，N沟道MIS晶体管具有 含有设置在基板和高k栅极绝缘膜之间的第一功函数调节元件的氧化硅膜或氧氮化硅膜，以及具有氧化硅膜或氮氧化硅膜的P沟道MIS晶体管， 其包括设置在高k栅极绝缘膜和栅电极之间的与N沟道MIS晶体管相同的第一功函数调节元件。