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公开(公告)号：US5146306A
公开(公告)日：1992-09-08
申请号：US638629
申请日：1991-01-08
IPC分类号： H03K19/003
CPC分类号： H03K19/00361
摘要： Slew-rate control is implemented in input/output device structures where MOSFETs are employed to switch the output signal. These MOSFETs each have a substrate, an insulating layer adjacent to the substrate and a strip of semiconductor material separated from the substrate by the insulating layer. The strip of semiconductor material functions as the gate of the MOSFET. The strip of semiconductor material does not form a closed loop. One end of the strip of a first transistor is connected to one end of the strip of the second transistor. Thus, the gates of the two transistors are placed in series so that they are not switched on at the same time. A delay is thereby automatically introduced between the switching on of the two transistors. The delay is controlled by placing metal straps across selected transistor gates to effectively bypass the delays caused by the current propagating through the gates. Further control of the delay is gained by use of a feedback signal to increase or decrease the current in the gates.
摘要翻译： 在使用MOSFET来切换输出信号的输入/输出器件结构中实现压摆率控制。 这些MOSFET各自具有基板，与基板相邻的绝缘层和通过绝缘层与基板分离的半导体材料条。 半导体材料条作为MOSFET的栅极起作用。 半导体材料条不形成闭环。 第一晶体管的条的一端连接到第二晶体管的条的一端。 因此，两个晶体管的栅极被串联放置，使得它们不被同时接通。 因此在两个晶体管的接通之间自动引入延迟。 通过将金属带放置在选定的晶体管栅极上来有效地绕过由栅极传播的电流引起的延迟来控制延迟。 通过使用反馈信号来增加或减少门中的电流来获得延迟的进一步控制。
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2.发明授权Digital output buffer and method with slew rate control and reduced crowbar current 失效数字输出缓冲器和方法，具有压摆率控制和减少撬棒电流
公开(公告)号：US5231311A
公开(公告)日：1993-07-27
申请号：US710838
申请日：1991-06-03
申请人： Thomas V. Ferry , Jamil Kawa , Kerry M. Pierce , William G. Walker , Michael A. Zampaglione , James S. Hsue
发明人： Thomas V. Ferry , Jamil Kawa , Kerry M. Pierce , William G. Walker , Michael A. Zampaglione , James S. Hsue
IPC分类号： H03K19/003
CPC分类号： H03K19/00361
摘要： A buffer characterized by a pull-up network and a pull-down network which are both coupled between an input and an output of the buffer. Each of the networks include a number of switch elements which can be sequentially turned on or off by means of an RC network to provide slew-rate control for the buffer. Preferably, each of the networks are associated with diode bypass networks to reduce crowbar current. In operation, both the pull-up network and the pull-down network turn on slowly but turn off very quickly due to the diode bypass networks.
摘要翻译： 一种缓冲器，其特征在于上拉网络和下拉网络，两者都耦合在缓冲器的输入和输出之间。 每个网络包括多个开关元件，其可以通过RC网络被顺序地接通或断开，以为缓冲器提供压摆率控制。 优选地，每个网络与二极管旁路网络相关联，以减少撬动电流。 在运行中，上拉网络和下拉网络均缓慢启动，但由于二极管旁路网络，它们都很快关闭。
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3.发明授权Method and apparatus for setting desired logic state at internal point of a select storage element 失效用于在选择存储元件的内部点处设置期望的逻辑状态的方法和装置
公开(公告)号：US5179534A
公开(公告)日：1993-01-12
申请号：US601969
申请日：1990-10-23
申请人： Kerry M. Pierce , Thomas V. Ferry
发明人： Kerry M. Pierce , Thomas V. Ferry
CPC分类号： H03K3/356086 , G11C11/41 , G11C29/04
摘要： An IC having a test grid structure including intersecting probe lines and control/sense lines is used to apply desired logic states directly to internal transmission paths of select storage elements. A switch is located at each intersection for conducting the desired logic state to the internal transmission path. To achieve overwriting and storage of the desired logic state, the conventional storage element is modified to include a transmission gate activated by an overwrite enable signal. The overwrite enable signal is defined by one or more probe lines. To overwrite the contents of a storage element, the storage element is selected by turning on the switch with a probe line coupled to such switch, while the included transmission gate is disabled by receiving the overwrite enable signal. The logic state of the control/sense line is conducted into the storage element to the included transmission gate where it overwrites the current contents and is stored.
摘要翻译： 具有包括相交探测线和控制/感测线的测试网格结构的IC被用于将期望的逻辑状态直接应用于选择的存储元件的内部传输路径。 开关位于每个十字路口处，以将期望的逻辑状态传送到内部传输路径。 为了实现所需逻辑状态的重写和存储，常规存储元件被修改为包括由覆盖使能信号激活的传输门。 覆盖使能信号由一个或多个探测线定义。 为了覆盖存储元件的内容，通过用耦合到这种开关的探针线接通开关来选择存储元件，同时通过接收覆盖使能信号来禁止包含的传输门。 控制/感测线的逻辑状态被传导到存储元件到所包含的传输门，其中它覆盖当前内容并被存储。
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4.发明授权
公开(公告)号：US5111075A
公开(公告)日：1992-05-05
申请号：US665385
申请日：1991-03-05
IPC分类号： H03K17/16 , H03K19/003 , H03K19/0175
CPC分类号： H03K19/00361
摘要： A buffer characterized by a pull-up network and a pull-down network which are both coupled between an input and an output of the buffer. Each of the networks include a number of switch elements which can be sequentially turned on or off by means of an RC network to provide slew-rate control for the buffer. Preferably, each of the networks are associated with diode bypass networks to reduce crowbar current. In operation, both the pull-up network and the pull-down network turn on slowly but turn off very quickly due to the diode bypass networks.
摘要翻译： 一种缓冲器，其特征在于上拉网络和下拉网络，两者都耦合在缓冲器的输入和输出之间。 每个网络包括多个开关元件，其可以通过RC网络被顺序地接通或断开，以为缓冲器提供压摆率控制。 优选地，每个网络与二极管旁路网络相关联，以减少撬动电流。 在运行中，上拉网络和下拉网络均缓慢启动，但由于二极管旁路网络，它们都很快关闭。
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5.发明授权Automatic optimization of a compiled memory structure based on user selected criteria 失效根据用户选择的标准自动优化编译的内存结构
公开(公告)号：US5625797A
公开(公告)日：1997-04-29
申请号：US148420
申请日：1993-11-03
CPC分类号： G11C7/1006
摘要： A block compiler system that allows a user to specify the total number of words and bits per word in a memory structure and to choose among alternative memory structures according to a user-selected criterion. In operation, the system varies the partitioning of memory address lines among column address lines and row address lines. Further, the system varies the internal memory structure according to a selected partitioning of memory address lines among column address lines and row address lines, and optimizes the memory structure based upon higher-level user-selected criteria.
摘要翻译： 一种块编译器系统，其允许用户指定存储器结构中每个字的单词和位的总数，并根据用户选择的标准在备选存储器结构中进行选择。 在操作中，系统改变列地址线和行地址线之间的存储器地址线的划分。 此外，系统根据列地址线和行地址线之间的存储器地址线的选择分区来改变内部存储器结构，并且基于更高级别的用户选择的标准优化存储器结构。
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