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    Semiconductor device having bar type active pattern
    1.
    发明授权
    Semiconductor device having bar type active pattern 有权
    具有棒式有源图案的半导体器件

    公开(公告)号：US08106464B2

    公开(公告)日：2012-01-31

    申请号：US12461500

    申请日：2009-08-13

    申请人： Keun-hwl Cho ,  Dong-won Kim ,  Jun Seo ,  Min-sang Kim ,  Sung-min Kim ,  Hyun-jun Bae ,  Ji-Myoung Lee

    发明人： Keun-hwl Cho ,  Dong-won Kim ,  Jun Seo ,  Min-sang Kim ,  Sung-min Kim ,  Hyun-jun Bae ,  Ji-Myoung Lee

    IPC分类号： H01L27/088

    CPC分类号： H01L29/66795 ,  H01L27/10814 ,  H01L27/10873 ,  H01L27/10879 ,  H01L29/785

    摘要： A semiconductor device having a bar type active pattern and a method of manufacturing the same are provided. The semiconductor device may include a semiconductor substrate having a semiconductor fin configured to protrude from a surface of the semiconductor substrate in a first direction, the semiconductor substrate having a first width and a second width crossing the first width, wherein the first width and the second width extend in a second direction. A plurality of active patterns may be arranged in the first direction with a separation gap from the semiconductor fin. A plurality of support patterns may be arranged between the semiconductor fin and one of the plurality of active patterns arranged closer to the semiconductor fin in the first direction, and between the plurality of active patterns arranged in the first direction to support the plurality of active patterns. A gate may be arranged to cross the plurality of active patterns in the second direction and to cover a portion of the at least one of the plurality of active patterns.

    摘要翻译： 提供了具有条形有源图案的半导体器件及其制造方法。 半导体器件可以包括具有半导体鳍片的半导体衬底，半导体鳍片被配置为在第一方向上从半导体衬底的表面突出，半导体衬底具有与第一宽度交叉的第一宽度和第二宽度，其中第一宽度和第二宽度 宽度在第二方向上延伸。 多个有源图案可以在第一方向上与半导体鳍片分离间隙布置。 多个支撑图案可以布置在半导体翅片与沿着第一方向布置得更靠近半导体鳍片的多个有源图案中的一个之间以及沿着第一方向布置的多个有源图案之间，以支撑多个有源图案 。 栅极可以布置成在第二方向上跨越多个有源图案并且覆盖多个有源图案中的至少一个的一部分。

    Semiconductor device having bar type active pattern
    2.
    发明申请
    Semiconductor device having bar type active pattern 有权
    具有棒式有源图案的半导体器件

    公开(公告)号：US20100059807A1

    公开(公告)日：2010-03-11

    申请号：US12461500

    申请日：2009-08-13

    申请人： Keun-hwl Cho ,  Dong-won Kim ,  Jun Seo ,  Min-sang Kim ,  Sung-min Kim ,  Hyun-jun Bae ,  Ji-Myoung Lee

    发明人： Keun-hwl Cho ,  Dong-won Kim ,  Jun Seo ,  Min-sang Kim ,  Sung-min Kim ,  Hyun-jun Bae ,  Ji-Myoung Lee

    IPC分类号： H01L27/108

    CPC分类号： H01L29/66795 ,  H01L27/10814 ,  H01L27/10873 ,  H01L27/10879 ,  H01L29/785

    摘要： A semiconductor device having a bar type active pattern and a method of manufacturing the same are provided. The semiconductor device may include a semiconductor substrate having a semiconductor fin configured to protrude from a surface of the semiconductor substrate in a first direction, the semiconductor substrate having a first width and a second width crossing the first width, wherein the first width and the second width extend in a second direction. A plurality of active patterns may be arranged in the first direction with a separation gap from the semiconductor fin. A plurality of support patterns may be arranged between the semiconductor fin and one of the plurality of active patterns arranged closer to the semiconductor fin in the first direction, and between the plurality of active patterns arranged in the first direction to support the plurality of active patterns. A gate may be arranged to cross the plurality of active patterns in the second direction and to cover a portion of the at least one of the plurality of active patterns.

    摘要翻译： 提供了具有条形有源图案的半导体器件及其制造方法。 半导体器件可以包括具有半导体鳍片的半导体衬底，半导体鳍片被配置为在第一方向上从半导体衬底的表面突出，半导体衬底具有与第一宽度交叉的第一宽度和第二宽度，其中第一宽度和第二宽度 宽度在第二方向上延伸。 多个有源图案可以在第一方向上与半导体鳍片分离间隙布置。 多个支撑图案可以布置在半导体翅片与沿着第一方向布置得更靠近半导体鳍片的多个有源图案中的一个之间以及沿着第一方向布置的多个有源图案之间，以支撑多个有源图案 。 栅极可以布置成在第二方向上跨越多个有源图案并且覆盖多个有源图案中的至少一个的一部分。

    Semiconductor devices including a transistor with elastic channel
    3.
    发明授权
    Semiconductor devices including a transistor with elastic channel 有权
    包括具有弹性通道的晶体管的半导体器件

    公开(公告)号：US08525147B2

    公开(公告)日：2013-09-03

    申请号：US13089477

    申请日：2011-04-19

    申请人： Ji-myoung Lee ,  Min-sang Kim ,  Dong-won Kim

    发明人： Ji-myoung Lee ,  Min-sang Kim ,  Dong-won Kim

    IPC分类号： H01L29/06

    CPC分类号： H01L27/105 ,  B82Y10/00 ,  H01L27/1021 ,  H01L27/115 ,  H01L27/1207 ,  H01L29/1606 ,  H01L29/42384 ,  H01L29/4908 ,  H01L29/66742 ,  H01L29/78606 ,  H01L29/78684 ,  H01L29/78696

    摘要： A semiconductor device that may control a formation of a channel is disclosed. The semiconductor device includes a gate region including a first area, an insulating layer disposed on portions of a top surface of the gate region corresponding to both ends portions of the first area, first and second electrodes formed on the insulating layer to be spaced apart from each other, an elastic conductive layer disposed between the first and second electrodes and the insulating layer and having a shape that varies according to an electrostatic force based on voltages applied to the first electrode, the second electrode, and the gate region, and a gate insulating region disposed between the elastic conductive layer and the first area of the gate region.

    摘要翻译： 公开了可以控制通道形成的半导体器件。 所述半导体器件包括栅极区域，所述栅极区域包括第一区域，绝缘层设置在与所述第一区域的两端部分对应的所述栅极区域的顶表面的部分上，形成在所述绝缘层上的第一和第二电极， 相互之间，设置在第一和第二电极与绝缘层之间并且具有根据施加到第一电极，第二电极和栅极区域的电压根据静电力而变化的形状的弹性导电层，以及栅极 绝缘区域设置在弹性导电层和栅极区域的第一区域之间。

    Semiconductor Devices Including a Transistor With Elastic Channel
    4.
    发明申请
    Semiconductor Devices Including a Transistor With Elastic Channel 有权
    包括具有弹性通道的晶体管的半导体器件

    公开(公告)号：US20110260136A1

    公开(公告)日：2011-10-27

    申请号：US13089477

    申请日：2011-04-19

    申请人： Ji-myoung Lee ,  Min-sang Kim ,  Dong-won Kim

    发明人： Ji-myoung Lee ,  Min-sang Kim ,  Dong-won Kim

    IPC分类号： H01L29/08 ,  B82Y99/00

    CPC分类号： H01L27/105 ,  B82Y10/00 ,  H01L27/1021 ,  H01L27/115 ,  H01L27/1207 ,  H01L29/1606 ,  H01L29/42384 ,  H01L29/4908 ,  H01L29/66742 ,  H01L29/78606 ,  H01L29/78684 ,  H01L29/78696

    摘要： A semiconductor device that may control a formation of a channel is disclosed. The semiconductor device includes a gate region including a first area, an insulating layer disposed on portions of a top surface of the gate region corresponding to both ends portions of the first area, first and second electrodes formed on the insulating layer to be spaced apart from each other, an elastic conductive layer disposed between the first and second electrodes and the insulating layer and having a shape that varies according to an electrostatic force based on voltages applied to the first electrode, the second electrode, and the gate region, and a gate insulating region disposed between the elastic conductive layer and the first area of the gate region.

    摘要翻译： 公开了可以控制通道形成的半导体器件。 所述半导体器件包括栅极区域，所述栅极区域包括第一区域，绝缘层设置在与所述第一区域的两端部分对应的所述栅极区域的顶表面的部分上，形成在所述绝缘层上的第一和第二电极， 相互之间，设置在第一和第二电极与绝缘层之间并且具有根据施加到第一电极，第二电极和栅极区域的电压根据静电力而变化的形状的弹性导电层和栅极 绝缘区域设置在弹性导电层和栅极区域的第一区域之间。

    Semiconductor device including FinFET having metal gate electrode and fabricating method thereof
    7.
    发明申请
    Semiconductor device including FinFET having metal gate electrode and fabricating method thereof 审中-公开
    包括具有金属栅电极的FinFET的半导体器件及其制造方法

    公开(公告)号：US20060175669A1

    公开(公告)日：2006-08-10

    申请号：US11339126

    申请日：2006-01-25

    申请人： Sung-min Kim ,  Dong-won Kim ,  Min-sang Kim ,  Eun-jung Yun

    发明人： Sung-min Kim ,  Dong-won Kim ,  Min-sang Kim ,  Eun-jung Yun

    IPC分类号： H01L29/76

    CPC分类号： H01L29/785 ,  H01L29/4908 ,  H01L29/66545 ,  H01L29/66795

    摘要： Provided are a semiconductor device including a FinFET having a metal gate electrode and a fabricating method thereof. The semiconductor device includes: an active area formed in a semiconductor substrate and protruding from a surface of the semiconductor substrate; a fin including first and second protrusions formed of a surface of the active area and parallel with each other based on a central trench formed in the active area and using upper surfaces and sides of the first and second protrusions as a channel area; a gate insulating layer formed on the active area including the fin; a metal gate electrode formed on the gate insulating layer; a gate spacer formed on a sidewall of the metal gate electrode; and a source and a drain formed in the active area beside both sides of the metal gate electrode. Here, the metal gate electrode comprises a barrier layer contacting the gate spacer and the gate insulating layer and a metal layer formed on the barrier layer.

    摘要翻译： 提供了包括具有金属栅极的FinFET的半导体器件及其制造方法。 半导体器件包括：形成在半导体衬底中并从半导体衬底的表面突出的有源区; 翅片，其包括由有源区域的表面形成的第一和第二突起，并且基于形成在有源区域中的中心沟槽并且使用第一和第二突起的上表面和侧面作为沟道区域彼此平行; 形成在包括所述鳍片的所述有源区域上的栅极绝缘层; 形成在所述栅极绝缘层上的金属栅电极; 形成在所述金属栅电极的侧壁上的栅极间隔; 以及在金属栅电极的两侧旁边的有源区域中形成的源极和漏极。 这里，金属栅电极包括与栅极间隔物和栅极绝缘层接触的阻挡层和形成在阻挡层上的金属层。

    Gate-all-around integrated circuit devices
    8.
    发明授权
    Gate-all-around integrated circuit devices 有权
    全能集成电路器件

    公开(公告)号：US08129800B2

    公开(公告)日：2012-03-06

    申请号：US11374644

    申请日：2006-03-13

    申请人： Eun-jung Yun ,  Sung-young Lee ,  Min-sang Kim ,  Sung-min Kim

    发明人： Eun-jung Yun ,  Sung-young Lee ,  Min-sang Kim ,  Sung-min Kim

    IPC分类号： H01L29/06

    CPC分类号： H01L29/78696 ,  H01L29/42392

    摘要： Gate-all-around integrated circuit devices include first and second source/drain regions on an active area of an integrated circuit substrate. The first and second source/drain regions form p-n rectifying junctions with the active area. A channel region extends between the first and second source/drain regions. An insulated gate electrode surrounds the channel region.

    摘要翻译： 栅极全能集成电路器件包括在集成电路衬底的有源区上的第一和第二源极/漏极区域。 第一和第二源极/漏极区域与有源区域形成p-n整流结。 沟道区域在第一和第二源极/漏极区域之间延伸。 绝缘栅极围绕通道区域。

    Semiconductor device with FinFET and method of fabricating the same
    9.
    发明授权
    Semiconductor device with FinFET and method of fabricating the same 有权
    具有FinFET的半导体器件及其制造方法

    公开(公告)号：US07972914B2

    公开(公告)日：2011-07-05

    申请号：US12477348

    申请日：2009-06-03

    申请人： Sung-min Kim ,  Min-sang Kim ,  Eun-jung Yun

    发明人： Sung-min Kim ,  Min-sang Kim ,  Eun-jung Yun

    IPC分类号： H01L21/338 ,  H01L21/336 ,  H01L21/3205

    CPC分类号： H01L29/785 ,  H01L29/42384 ,  H01L29/66795

    摘要： A FinFET semiconductor device has an active region formed of a semiconductor substrate and projecting from a surface of the substrate. A fin having a first projection and a second projection composed of the active region are arranged in parallel and at each side of a central trench formed in a central portion of the active region. Upper surfaces and side surfaces of the first projection and the second projection comprise a channel region. A channel ion implantation layer is provided at a bottom of the central trench and at a lower portion of the fin. A gate oxide layer is provided on the fin. A gate electrode is provided on the gate oxide layer. A source region and a drain region are provided in the active region at sides of the gate electrode. A method of forming such a device is also provided.

    摘要翻译： FinFET半导体器件具有由半导体衬底形成并从衬底的表面突出的有源区。 具有第一突起和由有源区组成的第二突起的翅片平行布置在形成在有源区的中心部分的中心沟槽的每一侧。 第一突起和第二突起的上表面和侧表面包括通道区域。 通道离子注入层设置在中央沟槽的底部和鳍片的下部。 在鳍片上设置栅极氧化层。 栅电极设置在栅氧化层上。 源极区域和漏极区域设置在栅电极侧的有源区域中。 还提供了一种形成这种装置的方法。

    Gate-all-around integrated circuit devices
    10.
    发明申请
    Gate-all-around integrated circuit devices 有权
    全能集成电路器件

    公开(公告)号：US20070045725A1

    公开(公告)日：2007-03-01

    申请号：US11374644

    申请日：2006-03-13

    申请人： Eun-jung Yun ,  Sung-young Lee ,  Min-sang Kim ,  Sung-min Kim

    发明人： Eun-jung Yun ,  Sung-young Lee ,  Min-sang Kim ,  Sung-min Kim

    IPC分类号： H01L29/94 ,  H01L29/76

    CPC分类号： H01L29/78696 ,  H01L29/42392

    摘要： Gate-all-around integrated circuit devices include first and second source/drain regions on an active area of an integrated circuit substrate. The first and second source/drain regions form p-n rectifying junctions with the active area. A channel region extends between the first and second source/drain regions. An insulated gate electrode surrounds the channel region.

    摘要翻译： 栅极全能集成电路器件包括在集成电路衬底的有源区上的第一和第二源极/漏极区域。 第一和第二源极/漏极区域与有源区域形成p-n整流结。 沟道区域在第一和第二源极/漏极区域之间延伸。 绝缘栅极围绕通道区域。