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公开(公告)号：US4864161A
公开(公告)日：1989-09-05
申请号：US190530
申请日：1988-05-05
IPC分类号： H03K3/037
CPC分类号： H03K3/037
摘要： A flip-flop-type circuit capable of operating either as a conventional D flip-flop or as a device which merely passes through the data applied to it (so-called "flow-through mode"). In the flow-through mode, the circuit has the additional capability of being able to latch in the data flowing through it at any time. Thus the circuit can also operate as a level-sensitive latch.
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2.发明授权Programmable logic devices with spare circuits for use in replacing defective circuits 失效具有备用电路的可编程逻辑器件用于更换有缺陷的电路
公开(公告)号：US4899067A
公开(公告)日：1990-02-06
申请号：US222832
申请日：1988-07-22
申请人： Hock-Chuen So , Sau-Ching Wong
发明人： Hock-Chuen So , Sau-Ching Wong
IPC分类号： H03K19/177 , G06F11/20
CPC分类号： H03K19/17748 , H03K19/17736 , H03K19/17764
摘要： A programmable logic device having a plurality of word lines and a plurality of bit lines, each of which is programmably interconnectable to at least one of the word lines for producing on each bit line a signal which is a logical function of the signal or signals on the word line or lines to which that bit line is interconnected. The logic device further includes at least one spare word line and/or bit line for use in the event that one of the regular lines of the same kind in defective. When the spare line is to be used, the device is preprogrammed to automatically redirect all signals intended for the bad line to another line, thereby putting the spare line into use. The signals thus automatically redirected include both the signals used during program mode to selectively interconnect the word lines and bit lines and the data signals subsequently processed during normal operation of the device.
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3.发明授权Programmable logic device with array blocks connected via programmable interconnect 失效具有可编程互连连接的阵列模块的可编程逻辑器件
公开(公告)号：US4871930A
公开(公告)日：1989-10-03
申请号：US190663
申请日：1988-05-05
IPC分类号： H01L21/82 , H03K19/177
CPC分类号： H03K19/17736 , H03K19/17704 , H03K19/17728 , H01L2224/05554 , H01L2224/49113
摘要： A programmable logic device having a relatively small number of programmable product terms ("P-terms") feeding each fixed combinatorial logic device, and additional "expander" programmable P-terms which do not directly feed a fixed device. Relatively simple logic functions can be performed by suitably programming the P-terms feeding the fixed devices. More complex logic functions can be performed by suitably programming the required number of expander P-terms, and then combining the outputs of those P-terms by means of another P-term. In addition, a programmable interconnect array is provided to allow certain inputs to the device to be applied to any programmable portion of the device, and also to allow the outputs of at least one of the fixed devices to be also applied to any programmable portion of the device.
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4.发明授权
公开(公告)号：US4912342A
公开(公告)日：1990-03-27
申请号：US407411
申请日：1989-09-14
IPC分类号： H03K19/177
CPC分类号： H03K19/17736 , H03K19/17704 , H03K19/1774 , H01L2224/05554 , H01L2224/49113
摘要： A programmable logic device having a relatively small number of programmable product terms ("P-terms") feeding each fixed combinatorial logic device, and additional "expander" programmable P-terms which do not directly feed a fixed device. Relatively simple logic functions can be performed by suitably programming the P-terms feeding the fixed devices. More complex logic functions can be performed by suitably programming the required number of expander P-terms, and then combining the outputs of those P-terms by means of another P-term. In addition, a programmable interconnect array is provided to allow certain inputs to the device to be applied to any programmable portion of the device, and also to allow the outputs of at least one of the fixed devices to be also applied to any programmable portion of the device.
摘要翻译： 具有相对较少数量的可编程产品术语（“P项”）供给每个固定组合逻辑器件的可编程逻辑器件，以及不直接馈送固定器件的附加“扩展器”可编程P项。 可以通过对馈送固定设备的P项进行适当编程来执行相对简单的逻辑功能。 可以通过适当地编程所需数量的扩展器P项来执行更复杂的逻辑功能，然后通过另外的P项组合这些P项的输出。 此外，提供可编程互连阵列以允许将装置的某些输入施加到装置的任何可编程部分，并且还允许至少一个固定装置的输出也被施加到装置的任何可编程部分 装置。
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5.发明授权High-density erasable programmable logic device architecture using multiplexer interconnections 失效使用多路复用器互连的高密度可擦除可编程逻辑器件架构
公开(公告)号：US5384499A
公开(公告)日：1995-01-24
申请号：US123435
申请日：1993-09-17
申请人： Bruce B. Pedersen , David Chiang , Francis B. Heile , Cameron McClintock , Hock-Chuen So , James A. Watson
发明人： Bruce B. Pedersen , David Chiang , Francis B. Heile , Cameron McClintock , Hock-Chuen So , James A. Watson
IPC分类号： H03K19/173 , H03K19/177
CPC分类号： H03K19/1776 , H03K19/1737 , H03K19/17728 , H03K19/17736 , H03K19/17764 , H03K19/17784 , H03K19/17792
摘要： A programmable logic device is presented comprising a global interconnect array whose lines are fed via programmable multiplexers to logic array blocks. The global interconnect array lines are fed to the multiplexers in a specific pattern which maximizes the user's ability to route a selected line to the output of a selected multiplexer, while at the same time maintaining higher speed and lower power consumption, and using less chip array than prior art programmable logic devices using programmable interconnect arrays based on erasable programmable read-only memories.
摘要翻译： 提出了一种可编程逻辑器件，其包括全局互连阵列，其线路经由可编程多路复用器馈送到逻辑阵列块。 全局互连阵列线以特定模式馈送到多路复用器，其最大化用户将所选线路路由到所选择的多路复用器的输出的能力，同时保持更高的速度和更低的功耗，并且使用更少的芯片阵列 比使用基于可擦除可编程只读存储器的可编程互连阵列的现有技术的可编程逻辑器件。
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6.发明授权High-density erasable programmable logic device architecture using multiplexer interconnections 失效高密度可擦除可编程逻辑器件结构使用多路复用器互连
公开(公告)号：US5241224A
公开(公告)日：1993-08-31
申请号：US691640
申请日：1991-04-25
申请人： Bruce B. Pedersen , David Chiang , Francis B. Heile , Cameron McClintock , Hock-Chuen So , James A. Watson
发明人： Bruce B. Pedersen , David Chiang , Francis B. Heile , Cameron McClintock , Hock-Chuen So , James A. Watson
IPC分类号： H03K19/173
CPC分类号： H03K19/1737
摘要： A programmable logic device is presented comprising a global interconnect array whose lines are fed via programmable multiplexers to logic array blocks. The global interconnect array lines are fed to the multiplexers in a specific pattern which maximizes the user's ability to route a selected line to the output of a selected multiplexer, while at the same time maintaining higher speed and lower power consumption, and using less chip array than prior art programmable logic devices using programmable interconnect arrays based on erasable programmable read-only memories.
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7.发明授权High-density erasable programmable logic device architecture using multiplexer interconnections 失效使用多路复用器互连的高密度可擦除可编程逻辑器件架构
公开(公告)号：US5268598A
公开(公告)日：1993-12-07
申请号：US043146
申请日：1993-03-31
申请人： Bruce B. Pedersen , David Chiang , Francis B. Heile , Cameron McClintock , Hock-Chuen So , James A. Watson
发明人： Bruce B. Pedersen , David Chiang , Francis B. Heile , Cameron McClintock , Hock-Chuen So , James A. Watson
IPC分类号： H03K19/173 , H03K19/177 , H03R19/177
CPC分类号： H03K19/1737 , H03K19/17728 , H03K19/17736 , H03K19/17764 , H03K19/17784 , H03K19/17792
摘要： A programmable logic device is presented comprising a global interconnect array whose lines are fed via programmable multiplexers to logic array blocks. The global interconnect array lines are fed to the multiplexers in a specific pattern which maximizes the user's ability to route a selected line to the output of a selected multiplexer, while at the same time maintaining higher speed and lower power consumption, and using less chip array than prior art programmable logic devices using programmable interconnect arrays based on erasable programmable read-only memories.
摘要翻译： 提出了一种可编程逻辑器件，其包括全局互连阵列，其线路经由可编程多路复用器馈送到逻辑阵列块。 全局互连阵列线以特定模式馈送到多路复用器，其最大化用户将所选线路路由到所选择的多路复用器的输出的能力，同时保持更高的速度和更低的功耗，并且使用更少的芯片阵列 比使用基于可擦除可编程只读存储器的可编程互连阵列的现有技术的可编程逻辑器件。
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