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1.发明授权Battery chargers, electrical systems, and rechargeable battery charging methods 有权电池充电器，电气系统和可充电电池充电方法公开(公告)号：US08598845B2
公开(公告)日：2013-12-03
申请号：US12426855
申请日：2009-04-20
申请人： Khoon Cheng Lim , Lap Wai Chow
发明人： Khoon Cheng Lim , Lap Wai Chow
IPC分类号： H02J7/00
CPC分类号： H02J7/0016 , H02J7/0075 , H02J7/0093 , H02J7/041 , H02J2007/105
摘要： Battery chargers, electrical systems, and rechargeable battery charging methods are described. According to one aspect, a battery charger includes charge circuitry configured to apply a plurality of main charging pulses of electrical energy to a plurality of rechargeable cells of a battery to charge the rechargeable cells during a common charge cycle of the battery and to apply a plurality of secondary charging pulses of electrical energy to less than all of the rechargeable cells of the battery during the common charge cycle of the battery to charge the less than all of the rechargeable cells.
摘要翻译： 描述了电池充电器，电气系统和可充电电池充电方法。 根据一个方面，电池充电器包括充电电路，其被配置为将电能的多个主充电脉冲施加到电池的多个可再充电电池，以在电池的公共充电周期期间对可充电电池充电并且施加多个 在电池的公共充电周期期间电能的次充电脉冲小于电池的所有可再充电电池，以对小于所有可再充电电池充电。
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2.发明申请Battery Chargers, Electrical Systems, and Rechargeable Battery Charging Methods 有权电池充电器，电气系统和充电电池充电方法公开(公告)号：US20100264879A1
公开(公告)日：2010-10-21
申请号：US12426855
申请日：2009-04-20
申请人： Khoon Cheng Lim , Lap Wai Chow
发明人： Khoon Cheng Lim , Lap Wai Chow
CPC分类号： H02J7/0016 , H02J7/0075 , H02J7/0093 , H02J7/041 , H02J2007/105
摘要： Battery chargers, electrical systems, and rechargeable battery charging methods are described. According to one aspect, a battery charger includes charge circuitry configured to apply a plurality of main charging pulses of electrical energy to a plurality of rechargeable cells of a battery to charge the rechargeable cells during a common charge cycle of the battery and to apply a plurality of secondary charging pulses of electrical energy to less than all of the rechargeable cells of the battery during the common charge cycle of the battery to charge the less than all of the rechargeable cells.
摘要翻译： 描述了电池充电器，电气系统和可充电电池充电方法。 根据一个方面，电池充电器包括充电电路，其被配置为将电能的多个主充电脉冲施加到电池的多个可再充电电池，以在电池的公共充电周期期间对可充电电池充电并且施加多个 在电池的公共充电周期期间电能的次充电脉冲小于电池的所有可再充电电池，以对小于所有可再充电电池充电。
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公开(公告)号：US08111089B2
公开(公告)日：2012-02-07
申请号：US12786205
申请日：2010-05-24
申请人： Ronald P. Cocchi , James P. Baukus , Bryan J. Wang , Lap Wai Chow , Paul Ouyang
发明人： Ronald P. Cocchi , James P. Baukus , Bryan J. Wang , Lap Wai Chow , Paul Ouyang
IPC分类号： H03K19/00 , H03K19/20 , H03K19/094
CPC分类号： H03K19/20
摘要： A logical building block and method of using the building block to design a logic cell library for CMOS (Complementary Metal Oxide Silicon) ASICs (Application Specific Integrated Circuits) is disclosed. Different logic gates, built with the same building block as described in this invention, will have the same schematics of transistor connection and also the same physical layout so that they appear to be physically identical under optical or electron microscopy. An ASIC designed from a library of such logic cells is strongly resistant to a reverse engineering attempt.
摘要翻译： 公开了使用构建块来设计用于CMOS（互补金属氧化物硅）ASIC（专用集成电路）的逻辑单元库的逻辑构建块和方法。 具有与本发明中描述的相同构造块构建的不同逻辑门将具有与晶体管连接相同的原理图以及相同的物理布局，使得它们在光学或电子显微镜下似乎在物理上相同。 由这种逻辑单元的库设计的ASIC非常耐逆向工程尝试。
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4.发明申请Programmable connection and isolation of active regions in an integrated circuit using ambiguous features to confuse a reverse engineer 失效使用模糊特征对集成电路中的有源区域进行可编程连接和隔离，从而使反向工程师混淆公开(公告)号：US20080079082A1
公开(公告)日：2008-04-03
申请号：US11855005
申请日：2007-09-13
申请人： William M. Clark , Lap Wai Chow , Gavin Harbison , Paul Ouyang
发明人： William M. Clark , Lap Wai Chow , Gavin Harbison , Paul Ouyang
CPC分类号： H01L27/0203 , H01L23/573 , H01L29/7833 , H01L2924/0002 , H01L2924/00
摘要： A technique for and structures for camouflaging an integrated circuit structure and strengthen its resistance to reverse engineering. A plurality of transistors are formed in a semiconductor substrate, at least some of the transistors being of the type having sidewall spacers with LDD regions formed under the sidewall spacers. Transistors are programmably interconnected with ambiguous interconnection features, the ambiguous interconnection features each comprising a channel formed in the semiconductor substrate with preferably the same dopant density as the LDD regions, with selected ones of the channels being formed of a conductivity type supporting electrical communication between interconnected active regions and with other selected ones of the channels being formed of a conductivity type inhibiting electrical communication but ambiguously appearing to a reverse engineer as supporting electrical communication.
摘要翻译： 用于伪装集成电路结构的技术和结构，并加强其对逆向工程的抵抗力。 在半导体衬底中形成多个晶体管，至少一些晶体管是具有侧壁间隔物的类型，其中LDD区形成在侧壁间隔件下方。 晶体管可编程地与不明确的互连特征相互连接，这些不明确的互连特征各自包括形成在半导体衬底中的通道，其优选地与LDD区域具有相同的掺杂剂密度，其中选定的通道由导电类型形成，支持互连 有源区域和其它选择的通道由导电类型抑制电气通信形成，但是对于逆向工程师而言，这些通道似乎是支持电气通信。
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5.发明授权Method and apparatus for camouflaging a standard cell based integrated circuit with micro circuits and post processing 有权用于对具有微电路和后处理的基于标准单元的集成电路进行伪装的方法和装置公开(公告)号：US08510700B2
公开(公告)日：2013-08-13
申请号：US13370118
申请日：2012-02-09
申请人： Ronald P. Cocchi , Lap Wai Chow , James P. Baukus , Bryan J. Wang
发明人： Ronald P. Cocchi , Lap Wai Chow , James P. Baukus , Bryan J. Wang
IPC分类号： G06F17/50
CPC分类号： G06F17/5072 , G06F17/5068 , G06F17/5077 , G06F21/14 , H01L27/0207 , H01L27/11807 , H03K19/17736
摘要： A method and apparatus for camouflaging an application specific integrated circuit (ASIC), wherein the ASIC comprises a plurality of interconnected functional logic is disclosed. The method adds functionally inert elements to the logical description or provides alternative definitions of standard logical cells to make it difficult for reverse engineering programs to be used to discover the circuit's function. Additionally, post processing may be performed on GDS layers to provide a realistic fill of the empty space so as to resemble structural elements found in a functional circuit.
摘要翻译： 一种用于伪装专用集成电路（ASIC）的方法和装置，其中所述ASIC包括多个互连的功能逻辑。 该方法将功能上的惰性元件添加到逻辑描述中，或提供标准逻辑单元的替代定义，使得难以使用逆向工程程序来发现电路的功能。 此外，可以在GDS层上执行后处理以提供空白空间的实际填充，以便类似于在功能电路中找到的结构元素。
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6.发明授权Programmable connection and isolation of active regions in an integrated circuit using ambiguous features to confuse a reverse engineer 失效使用模糊特征对集成电路中的有源区域进行可编程连接和隔离，从而使反向工程师混淆公开(公告)号：US08168487B2
公开(公告)日：2012-05-01
申请号：US11855005
申请日：2007-09-13
IPC分类号： H01L21/335
CPC分类号： H01L27/0203 , H01L23/573 , H01L29/7833 , H01L2924/0002 , H01L2924/00
摘要： A technique for and structures for camouflaging an integrated circuit structure and strengthen its resistance to reverse engineering. A plurality of transistors are formed in a semiconductor substrate, at least some of the transistors being of the type having sidewall spacers with LDD regions formed under the sidewall spacers. Transistors are programmably interconnected with ambiguous interconnection features, the ambiguous interconnection features each comprising a channel formed in the semiconductor substrate with preferably the same dopant density as the LDD regions, with selected ones of the channels being formed of a conductivity type supporting electrical communication between interconnected active regions and with other selected ones of the channels being formed of a conductivity type inhibiting electrical communication but ambiguously appearing to a reverse engineer as supporting electrical communication.
摘要翻译： 用于伪装集成电路结构的技术和结构，并加强其对逆向工程的抵抗力。 在半导体衬底中形成多个晶体管，至少一些晶体管是具有侧壁间隔物的类型，其中LDD区形成在侧壁间隔物下。 晶体管可编程地与不明确的互连特征相互连接，这些不明确的互连特征各自包括形成在半导体衬底中的通道，其优选地与LDD区域具有相同的掺杂剂密度，其中选定的通道由导电类型形成，支持互连 有源区域和其它选择的通道由导电类型抑制电气通信形成，但是对于逆向工程师而言，这些通道似乎是支持电气通信。
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公开(公告)号：US20100301903A1
公开(公告)日：2010-12-02
申请号：US12786205
申请日：2010-05-24
申请人： Ronald P. Cocchi , James P. Baukus , Bryan J. Wang , Lap Wai Chow , Paul Ouyang
发明人： Ronald P. Cocchi , James P. Baukus , Bryan J. Wang , Lap Wai Chow , Paul Ouyang
IPC分类号： H03K19/0948 , H03K19/094
CPC分类号： H03K19/20
摘要： A logical building block and method of using the building block to design a logic cell library for CMOS (Complementary Metal Oxide Silicon) ASICs (Application Specific Integrated Circuits) is disclosed. Different logic gates, built with the same building block as described in this invention, will have the same schematics of transistor connection and also the same physical layout so that they appear to be physically identical under optical or electron microscopy. An ASIC designed from a library of such logic cells is strongly resistant to a reverse engineering attempt.
摘要翻译： 公开了使用构建块来设计用于CMOS（互补金属氧化物硅）ASIC（专用集成电路）的逻辑单元库的逻辑构建块和方法。 具有与本发明中描述的相同构造块构建的不同逻辑门将具有与晶体管连接相同的原理图以及相同的物理布局，使得它们在光学或电子显微镜下似乎在物理上相同。 由这种逻辑单元的库设计的ASIC非常耐逆向工程尝试。
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公开(公告)号：US5930663A
公开(公告)日：1999-07-27
申请号：US76012
申请日：1998-05-11
IPC分类号： H01L21/3205 , G06F21/06 , G11C7/24 , H01L21/82 , H01L21/822 , H01L23/52 , H01L27/02 , H01L27/04 , H01L21/265
CPC分类号： H01L23/573 , G11C7/24 , H01L27/02 , H01L2924/0002
摘要： An integrated digital circuit is protected from reverse engineering by fabricating all transistors of like conductivity with a common size and geometric layout, providing a common layout for different logic cells, connecting doped circuit elements of like conductivity with electrically conductive doped implants in the substrate rather than metalized interconnections, and providing non-functional apparent interconnections that are interrupted by non-discernable channel stops so that all cells falsely appear to have a common interconnection scheme. The camouflage is enhanced by providing a uniform pattern of metal leads over the transistor array, with a uniform pattern of heavily doped implant taps from the transistors for connection to the leads; undesired tap-lead connections are blocked by channel stops.
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9.发明授权Programmable connection and isolation of active regions in an integrated circuit using ambiguous features to confuse a reverse engineer 失效使用模糊特征对集成电路中的有源区域进行可编程连接和隔离，从而使反向工程师混淆公开(公告)号：US08564073B1
公开(公告)日：2013-10-22
申请号：US13423155
申请日：2012-03-16
IPC分类号： H01L29/66
CPC分类号： H01L27/0203 , H01L23/573 , H01L29/7833 , H01L2924/0002 , H01L2924/00
摘要： A technique for and structures for camouflaging an integrated circuit structure and strengthen its resistance to reverse engineering. A plurality of transistors are formed in a semiconductor substrate, at least some of the transistors being of the type having sidewall spacers with LDD regions formed under the sidewall spacers. Transistors are programmably interconnected with ambiguous interconnection features, the ambiguous interconnection features each comprising a channel formed in the semiconductor substrate with preferably the same dopant density as the LDD regions, with selected ones of the channels being formed of a conductivity type supporting electrical communication between interconnected active regions and with other selected ones of the channels being formed of a conductivity type inhibiting electrical communication but ambiguously appearing to a reverse engineer as supporting electrical communication.
摘要翻译： 用于伪装集成电路结构的技术和结构，并加强其对逆向工程的抵抗力。 在半导体衬底中形成多个晶体管，至少一些晶体管是具有侧壁间隔物的类型，其中LDD区形成在侧壁间隔物下。 晶体管可编程地与不明确的互连特征相互连接，这些不明确的互连特征各自包括形成在半导体衬底中的通道，其优选地与LDD区域具有相同的掺杂剂密度，其中选定的通道由导电类型形成，支持互连 有源区域和其它选择的通道由导电类型抑制电气通信形成，但是对于逆向工程师而言，这些通道似乎是支持电气通信。
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10.发明授权Digital circuit with transistor geometry and channel stops providing camouflage against reverse engineering 有权具有晶体管几何形状和通道的数字电路停止提供防止逆向工程的伪装
公开(公告)号：US06064110A
公开(公告)日：2000-05-16
申请号：US243855
申请日：1999-02-03
IPC分类号： H01L21/3205 , G06F21/06 , G11C7/24 , H01L21/82 , H01L21/822 , H01L23/52 , H01L27/02 , H01L27/04 , H01L23/58
CPC分类号： H01L23/573 , G11C7/24 , H01L27/02 , H01L2924/0002
摘要： An integrated digital circuit is protected from reverse engineering by fabricating all transistors of like conductivity with a common size and geometric layout, providing a common layout for different logic cells, connecting doped circuit elements of like conductivity with electrically conductive doped implants in the substrate rather than metalized interconnections, and providing non-functional apparent interconnections that are interrupted by non-discernable channel stops so that all cells falsely appear to have a common interconnection scheme. The camouflage is enhanced by providing a uniform pattern of metal leads over the transistor array, with a uniform pattern of heavily doped implant taps from the transistors for connection to the leads; undesired tap-lead connections are blocked by channel stops.
摘要翻译： 通过制造具有共同尺寸和几何布局的所有具有类似导电性的晶体管来保护集成数字电路免受逆向工程，为不同的逻辑单元提供通用布局，将类似导电性的掺杂电路元件与衬底中的导电掺杂植入物连接起来，而不是 金属化互连，并且提供由不可识别的通道停止中断的非功能性视在互连，使得所有单元看起来具有共同的互连方案。 通过在晶体管阵列上提供均匀的金属引线图案来增强伪装，晶体管具有均匀的重掺杂注入阱图案，用于连接到引线; 通道停止阻塞不需要的抽头引线连接。
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