公开(公告)号：US06734458B2

公开(公告)日：2004-05-11

申请号：US10029390

申请日：2001-12-28

申请人： Ki Seog Kim ,  Young Seon You ,  Keun Woo Lee ,  Sung Kee Park

发明人： Ki Seog Kim ,  Young Seon You ,  Keun Woo Lee ,  Sung Kee Park

IPC分类号： H01L2358

CPC分类号： H01L23/544 ,  H01L2223/54453 ,  H01L2924/0002 ,  H01L2924/00

摘要： The present invention relates to a test pattern for measuring a contact resistance and method of manufacturing the same. In order to confirm that a contact resistance suitable for a semiconductor device before an actual process for manufacturing the device is performed, the present invention designs a test pattern for measuring the contact resistance depending on a design rule of a line contact actually applied to an actual device. At this time, a first line contact region and a second line contact region are formed between a word line so that a line contact region can form a pair; a plurality of sources are formed in the first line contact region and a plurality of sources are formed in the second line contact region wherein neighboring sources are connected by diffusion layers so that the first line contact region and the second line contact region can be electrically connected; and a plurality of line contact patterns are formed so that the plurality of the sources can be electrically connected by every two in each of the first and second line contact regions wherein the line contact pattern formed in the first line contact region and the line contact pattern formed in the second line contact region are alternately positioned. Therefore, the present invention can allow current for measuring the resistance sequentially along the first line contact region and the second line contact region to measure the line contact resistance in which the contact resistance in every source portion is considered.

摘要翻译： 本发明涉及一种测量接触电阻​​的测试图案及其制造方法。 为了确认在进行用于制造该器件的实际工艺之前适用于半导体器件的接触电阻，本发明根据实际应用于实际的线路接触的设计规则来设计用于测量接触电阻​​的测试图案 设备。 此时，在字线之间形成第一线接触区域和第二线路接触区域，使得线路接触区域可以形成一对; 多个源极形成在第一线路接触区域中，并且多个源极形成在第二线路接触区域中，其中相邻源极通过扩散层连接，使得第一线路接触区域和第二线路接触区域可以电连接 ; 并且形成多个线接触图案，使得多个源可以在形成在第一线接触区域中的线接触图案和线接触图案的第一和第二线路接触区域中的每一个中每两个电连接一次 形成在第二线接触区域中的交替位置。 因此，本发明可以允许沿着第一线路接触区域和第二线路接触区域依次测量电阻的电流来测量考虑到每个源极部分中的接触电阻的线路接触电阻。

公开(公告)号：US06204125B1

公开(公告)日：2001-03-20

申请号：US09605632

申请日：2000-06-28

申请人： Keun Woo Lee ,  Ki Seog Kim ,  Jin Shin ,  Sung Kee Park

发明人： Keun Woo Lee ,  Ki Seog Kim ,  Jin Shin ,  Sung Kee Park

IPC分类号： H01L218247

CPC分类号： H01L27/11521 ,  H01L21/28273

摘要： The present invention relates to a method of forming a gate in a stack gate flash EEPROM cell. In order to preventing a lateral bird's beak from occurring in an ONO dielectric layer during a reoxidation process to be performed after a formation of a cell gate having a stack structure formed by stacking a floating gate, an ONO dielectric layer and a control gate, an oxide layer and a nitride layer are sequentially formed on an entire structure before the reoxidation and after a formation of the cell gate. The oxide layer serves to reduce a stress in depositing the nitride layer, and the nitride layer serves to prevent an occurrence of the lateral bird's beak of the ONO dielectric layer during the reoxidation process. Accordingly, the present invention prevents the lateral bird's beak of the ONO dielectric layer, thereby improving a speed of cell erase operation.

摘要翻译： 本发明涉及一种在堆叠栅极快闪EEPROM单元中形成栅极的方法。 为了防止在形成具有通过堆叠浮栅，ONO电介质层和控制栅形成的堆叠结构的电池栅极的再氧化工艺期间在ONO电介质层中发生侧面鸟嘴， 氧化层和氮化物层在再氧化之前和电池栅极形成之后的整个结构上依次形成。 氧化物层用于减少沉积氮化物层的应力，并且氮化物层用于在再氧化过程期间防止ONO电介质层的侧面鸟喙的发生。 因此，本发明能够防止ONO电介质层的横向鸟嘴，从而提高电池擦除操作的速度。

公开(公告)号：US07099198B2

公开(公告)日：2006-08-29

申请号：US10968687

申请日：2004-10-19

申请人： Ki Seog Kim ,  Keun Woo Lee ,  Sung Kee Park ,  Yoo Nam Jeon

发明人： Ki Seog Kim ,  Keun Woo Lee ,  Sung Kee Park ,  Yoo Nam Jeon

IPC分类号： G11C16/06

CPC分类号： G11C16/08 ,  G11C16/16 ,  G11C29/70

摘要： A row decoder in a flash memory comprises a first switch to selectively couple a word line to a first voltage terminal, and a second switch to selectively couple the word line to a second voltage terminal. The row decoder also comprises a third switch to selectively couple the word line to a third voltage terminal.

摘要翻译： 闪速存储器中的行解码器包括用于选择性地将字线耦合到第一电压端子的第一开关和用于选择性地将字线耦合到第二电压端子的第二开关。 行解码器还包括用于选择性地将字线耦合到第三电压端子的第三开关。

公开(公告)号：US06819597B2

公开(公告)日：2004-11-16

申请号：US10614229

申请日：2003-07-07

申请人： Ki Seog Kim ,  Keun Woo Lee ,  Sung Kee Park ,  Yoo Nam Jeon

发明人： Ki Seog Kim ,  Keun Woo Lee ,  Sung Kee Park ,  Yoo Nam Jeon

IPC分类号： G11C1606

CPC分类号： G11C16/08 ,  G11C16/16 ,  G11C29/70

摘要： Disclosed are a row decoder in a flash memory and erasing method in a flash memory cell using the same. The row decoder comprises a PMOS transistor having a gate electrode for receiving a first input signal as an input and connected between a first power supply terminal and a first node, a first NMOS transistor having a gate electrode for receiving the first input signal as an input and connected between the first node and a second node, a second NMOS transistor having a gate electrode for receiving the second input signal as an input and connected between the second node and a ground terminal, and a switching means having a gate electrode for receiving the third input signal as an input and connected between the second node and a second power supply terminal, wherein the first node is connected to word lines.

摘要翻译： 本发明公开了一种闪速存储器中的行解码器和使用其的擦除方法。 行解码器包括具有用于接收第一输入信号作为输入并连接在第一电源端子和第一节点之间的栅电极的PMOS晶体管，具有用于接收第一输入信号作为输入的栅电极的第一NMOS晶体管 并连接在第一节点和第二节点之间的第二NMOS晶体管，具有用于接收第二输入信号作为输入并连接在第二节点和接地端子之间的栅电极的第二NMOS晶体管，以及具有栅电极的开关装置， 第三输入信号作为输入并连接在第二节点和第二电源端子之间，其中第一节点连接到字线。

公开(公告)号：US06743676B2

公开(公告)日：2004-06-01

申请号：US10286980

申请日：2002-11-04

申请人： Sung Kee Park ,  Ki Seog Kim ,  Keun Woo Lee ,  Keon Soo Shim

发明人： Sung Kee Park ,  Ki Seog Kim ,  Keun Woo Lee ,  Keon Soo Shim

IPC分类号： H01L21336

CPC分类号： H01L27/11521 ,  H01L27/115

摘要： The present invention relates to a method of forming a floating gate in a flash memory device. Upon formation of a device isolation film, a space of a lower polysilicon layer for a floating gate is defined, a bird's beak is formed on an internal surface of a trench by subsequent well sacrificial oxidization process and well oxidization process and an upper polysilicon layer for a floating gate is then formed, so that the space of the floating gate is formed. Therefore, the present invention can reduce the cost since a mask process is not required compared to an existing stepper method and the process cost since a planarization process using chemical mechanical polishing process (CMP) is not required compared to the self-aligned floating mode.

摘要翻译： 本发明涉及一种在闪速存储器件中形成浮动栅极的方法。 在形成器件隔离膜时，限定用于浮置栅极的下多晶硅层的空间，通过随后的良好牺牲氧化过程和阱氧化过程在沟槽的内表面上形成鸟嘴，以及上部多晶硅层 形成浮栅，从而形成浮栅的空间。 因此，与现有步进法相比，本发明可以降低成本，因为与自对准浮动模式相比，不需要使用化学机械抛光工艺（CMP）的平坦化处理，因此与现有的步进方法和工艺成本相比不需要掩模处理。

公开(公告)号：US06316313B1

公开(公告)日：2001-11-13

申请号：US09717002

申请日：2000-11-22

申请人： Sung Kee Park ,  Ki Seog Kim ,  Sang Hoan Chang ,  Keun Woo Lee

发明人： Sung Kee Park ,  Ki Seog Kim ,  Sang Hoan Chang ,  Keun Woo Lee

IPC分类号： H01L218247

CPC分类号： H01L27/112

摘要： There is disclosed a method of manufacturing a flash memory device. In order to solve the problems that a well resistance and a parasitic capacitance are great and the erase speed of a device is slow in case of the conventional flash memory device, the present invention forms a well region of a sector unit by use of a metal silicide layer and defines an unit cell by use of a ploysilicon layer. Thus, it can reduce the well resistance and the parasitic capacitance. Also, it can improve the operating speed of the device and can reduce the manufacturing cost by allowing the erase operation of a cell unit.

摘要翻译： 公开了一种制造闪速存储器件的方法。 为了解决现有的闪速存储器件的情况下阱电阻和寄生电容大的问题以及器件的擦除速度较慢的问题，本发明通过使用金属形成扇区单元的阱区 硅化物层并且通过使用合金层来限定晶胞。 因此，它可以降低阱电阻和寄生电容。 此外，它可以提高装置的操作速度，并且可以通过允许单元单元的擦除操作来降低制造成本。

公开(公告)号：US06717848B2

公开(公告)日：2004-04-06

申请号：US10287779

申请日：2002-11-05

申请人： Ki Seog Kim ,  Young Seon You ,  Won Yeol Choi ,  Yoo Nam Jeon

发明人： Ki Seog Kim ,  Young Seon You ,  Won Yeol Choi ,  Yoo Nam Jeon

IPC分类号： G11C1604

CPC分类号： G11C16/28 ,  G11C11/5642

摘要： The present invention relates to a sensing circuit in a multi-level flash memory cell capable of exactly sensing a state of the multi-level flash memory cell by sensing four states of the multi-level flash memory cell based on first through third reference cells. The first reference cell has a threshold voltage by which a program or erase state of a floating gate can be determined in a state that a capacitor of the multi-level flash memory cell is discharged, a second reference cell has a threshold voltage by which a charge or discharge state of the capacitor can be determined with the floating gate of the multi-level flash memory cell being at a discharge state, and a third reference cell has a threshold voltage by which a charge or discharge state of the capacitor can be determined with the floating gate of the multi-level flash memory cell being at a program state.

摘要翻译： 本发明涉及一种多级闪存单元中的感测电路，其能够通过基于第一至第三参考单元感测多电平闪存单元的四个状态来精确地感测多电平闪存单元的状态。 第一参考单元具有阈值电压，通过该阈值电压可以在多电平闪存单元的电容器放电的状态下确定浮置栅极的编程或擦除状态，第二参考单元具有阈值电压， 电容器的充电或放电状态可以通过多电平闪速存储单元的浮置栅极处于放电状态来确定，并且第三参考单元具有可以确定电容器的充电或放电状态的阈值电压 多级闪存单元的浮动栅极处于编程状态。

公开(公告)号：US07848150B2

公开(公告)日：2010-12-07

申请号：US12055641

申请日：2008-03-26

申请人： Keun Woo Lee ,  Ki Seog Kim

发明人： Keun Woo Lee ,  Ki Seog Kim

IPC分类号： G11C11/34 ,  G11C16/06

CPC分类号： G11C16/26 ,  G11C16/0483 ,  G11C16/349

摘要： A flash memory device and a method of operating the same is disclosed, in which the conditions of voltage (or current) applied during the reading operation are differently adjusted according to an accumulated number of times of a programming operation, an erasing operation or a reading operation (an accumulated number of operation cycle). Even if a level of the threshold voltage is changed to a level which differs from that of the target voltage by an increase of the accumulated number of operation cycle regardless of the programming operation (or the erasing operation) being normally performed, the reliability of the reading operation can be enhanced to prevent a malfunction of the memory cell from being generated.

摘要翻译： 公开了一种闪速存储装置及其操作方法，其中根据编程操作，擦除操作或读取的累积次数，不同地调整在读取操作期间施加的电压（或电流）的条件 操作（累计操作周期数）。 即使通过正常执行编程操作（或擦除操作），通过累积操作周期数的增加，阈值电压的电平变化到与目标电压的电平不同的电平，则可靠性 可以增强读取操作以防止生成存储器单元的故障。

公开(公告)号：US06391665B1

公开(公告)日：2002-05-21

申请号：US09722112

申请日：2000-11-27

申请人： Sang Hoan Chang ,  Ki Seog Kim ,  Jin Shin ,  Keun Woo Lee

发明人： Sang Hoan Chang ,  Ki Seog Kim ,  Jin Shin ,  Keun Woo Lee

IPC分类号： H01L21336

CPC分类号： H01L27/11521 ,  G11C16/04 ,  G11C29/50 ,  G11C29/50008 ,  G11C2029/5006 ,  H01L21/76895 ,  H01L27/115

摘要： There is disclosed a method of monitoring a source contact in a flash memory by which whether a source contact having a narrow contact area contacts or not can be easily monitored using over-erase cell characteristic in a flash cell, in a flash memory device in which a source line is formed by a local interconnection method. In the present invention, in order to monitor a contact state at source contacts, the same voltage to the erase condition of a cell is applied to respective terminals (VG terminal, VD terminal, VS terminal and VSS terminal) wherein all the electrons existing at a floating gate in all the cells connected to the VS terminal and VSS terminal become turned on so that they can be over-erased. On the other hands, as electrons existing at the floating gate in two cells shared by any source contacts having a defect contact are not erased, the cells remain turn-off. In this state, if test voltages (VG=0V, VD

摘要翻译： 公开了一种监视闪速存储器中的源极触点的方法，通过该闪光存储器中的源极触点可以容易地利用闪存单元中的过擦除单元特性来容易地监视具有窄接触区域的源极触点的触点， 源线由本地互连方式形成。 在本发明中，为了监测源极触点的接触状态，将与电池的擦除状态相同的电压施加到各个端子（VG端子，VD端子，VS端子和VSS端子），其中所有电子存在于 连接到VS端子和VSS端子的所有单元中的浮动栅极变为导通，使得它们可能被过擦除。 另一方面，由于存在于由具有缺陷接触的任何源极触点共享的两个电池中的浮动栅极处的电子不被擦除，所以电池保持关断。 在这种状态下，如果施加了测试电压（VG = 0V，VD <5V，VS =浮动，VSS =接地），则在具有接触缺陷的部分中，从VD端子到VSS端子的电流断开，从而允许 要监控的源触点的接触状态。

公开(公告)号：US20100178745A1

公开(公告)日：2010-07-15

申请号：US12731594

申请日：2010-03-25

申请人： Yoo Nam Jeon ,  Ki Seog Kim

发明人： Yoo Nam Jeon ,  Ki Seog Kim

IPC分类号： H01L21/336

CPC分类号： G11C16/0483 ,  G11C16/3418 ,  G11C16/3427 ,  H01L27/11521 ,  H01L27/11524

摘要： The present invention relates to a flash memory device and a fabrication method thereof. A trench may be formed within a junction region between word lines by etching a semiconductor substrate between not only a word line and a select line, but also between adjacent word lines. Accordingly, the occurrence of a program disturbance phenomenon can be prevented as the injection of hot carriers into a program-inhibited cell is minimized in a program operation.

摘要翻译： 本发明涉及闪速存储器件及其制造方法。 可以在字线之间的接合区域中形成沟槽，通过不仅在字线和选择线之间，而且在相邻字线之间蚀刻半导体衬底。 因此，由于在程序操作中将热载流子注入到程序禁止单元中被最小化，所以可以防止编程干扰现象的发生。