公开(公告)号：US20090052243A1

公开(公告)日：2009-02-26

申请号：US12222895

申请日：2008-08-19

申请人： Ki-tae Park ,  Ki-nam Kim ,  Yeong-taek Lee

发明人： Ki-tae Park ,  Ki-nam Kim ,  Yeong-taek Lee

IPC分类号： G11C16/04 ,  G11C16/06

CPC分类号： G11C11/5628 ,  G11C16/3418 ,  G11C2211/5621

摘要： A method of controlling data includes, with respect to non-volatile memory cells connected to bit lines corresponding to a first bit line group, first controlling data written to the non-volatile memory cells by varying a control voltage, and, with respect to non-volatile memory cells connected to bit lines corresponding to a second bit line group, second controlling data written to the non-volatile memory cells by varying a control voltage. The controlling may include reading or verifying. Before verification, the method may include writing data to the non-volatile memory cells.

摘要翻译： 控制数据的方法包括：相对于与第一位线组对应的位线连接的非易失性存储单元，通过改变控制电压来首先控制写入非易失性存储单元的数据， 连接到与第二位线组对应的位线的非易失性存储单元，通过改变控制电压将第二控制数据写入非易失性存储单元。 控制可能包括阅读或验证。 在验证之前，该方法可以包括向非易失性存储器单元写入数据。

公开(公告)号：US08305816B2

公开(公告)日：2012-11-06

申请号：US12222895

申请日：2008-08-19

申请人： Ki-tae Park ,  Ki-nam Kim ,  Yeong-taek Lee

发明人： Ki-tae Park ,  Ki-nam Kim ,  Yeong-taek Lee

IPC分类号： G11C16/04

CPC分类号： G11C11/5628 ,  G11C16/3418 ,  G11C2211/5621

摘要： A method of controlling data includes, with respect to non-volatile memory cells connected to bit lines corresponding to a first bit line group, first controlling data written to the non-volatile memory cells by varying a control voltage, and, with respect to non-volatile memory cells connected to bit lines corresponding to a second bit line group, second controlling data written to the non-volatile memory cells by varying a control voltage. The controlling may include reading or verifying. Before verification, the method may include writing data to the non-volatile memory cells.

摘要翻译： 控制数据的方法包括：相对于与第一位线组对应的位线连接的非易失性存储单元，通过改变控制电压来首先控制写入非易失性存储单元的数据， 连接到与第二位线组对应的位线的非易失性存储单元，通过改变控制电压将第二控制数据写入非易失性存储单元。 控制可能包括阅读或验证。 在验证之前，该方法可以包括向非易失性存储器单元写入数据。

公开(公告)号：US07940578B2

公开(公告)日：2011-05-10

申请号：US12320003

申请日：2009-01-14

申请人： Myoung-gon Kang ,  Yeong-taek Lee ,  Ki-tae Park ,  Doo-gon Kim

发明人： Myoung-gon Kang ,  Yeong-taek Lee ,  Ki-tae Park ,  Doo-gon Kim

IPC分类号： G11C5/14

CPC分类号： G11C16/3418 ,  G11C7/02 ,  G11C8/10 ,  G11C16/0483 ,  G11C16/3427 ,  G11C17/16 ,  G11C29/52

摘要： A flash memory device includes first and second memory cell array blocks and a row decoder coupled to the first memory cell array block and the second memory cell array block. The row decoder includes a block decoder, a single high voltage level shifter that is coupled to both the first and second memory cell array blocks, the single high voltage level shifter configured to provide a block wordline signal of a high voltage to the first and second memory array blocks in response to a block selection signal received from the block decoder, a first pass transistor unit, and a second pass transistor unit.

摘要翻译： 闪速存储器件包括第一和第二存储单元阵列块以及耦合到第一存储单元阵列块和第二存储单元阵列块的行解码器。 行解码器包括块解码器，耦合到第一和第二存储单元阵列块的单个高电压电平移位器，该单个高电压电平移位器被配置为向第一和第二存储单元阵列块提供高电压的块字线信号 存储器阵列块，响应于从块解码器接收的块选择信号，第一传输晶体管单元和第二传输晶体管单元。

公开(公告)号：US08116131B2

公开(公告)日：2012-02-14

申请号：US12264353

申请日：2008-11-04

申请人： Ki-tae Park ,  Yeong-taek Lee

发明人： Ki-tae Park ,  Yeong-taek Lee

IPC分类号： G11C11/34

CPC分类号： G11C16/3418

摘要： Provided is a method of programming a non-volatile memory device. The method includes applying a first programming pulse to a corresponding wordline of the non-volatile memory device, applying a second programming pulse to the wordline, wherein a voltage of the second programming pulse is different from that of the first programming pulse, and applying voltages to each bitline connected to the wordline, the voltages applied to each of the bitlines are different from each other according to a plurality of bit values to be programmed to corresponding memory cells in response to the first programming pulse or the second programming pulse.

摘要翻译： 提供了一种对非易失性存储器件进行编程的方法。 该方法包括将第一编程脉冲施加到非易失性存储器件的对应字线，向第二编程脉冲施加第二编程脉冲，其中第二编程脉冲的电压与第一编程脉冲的电压不同，并施加电压 对于连接到字线的每个位线，施加到每个位线的电压根据要响应于第一编程脉冲或第二编程脉冲被编程到相应存储器单元的多个位值而彼此不同。

公开(公告)号：US20080310230A1

公开(公告)日：2008-12-18

申请号：US12136933

申请日：2008-06-11

申请人： Doo-gon Kim ,  Ki-tae Park ,  Yeong-taek Lee

发明人： Doo-gon Kim ,  Ki-tae Park ,  Yeong-taek Lee

IPC分类号： G11C16/06

CPC分类号： G11C16/3418

摘要： Flash memory devices are provided including a plurality of layers stacked vertically. Each of the plurality of layers include a plurality of memory cells. A row decoder is electrically coupled to the plurality of layers and configured to supply a wordline voltage to the plurality of layers. Memory cells provided in at least two layers of the plurality of layers belong to a same memory block and wordlines associated with the memory cells in the at least two layers of the plurality of layers are electrically coupled.

摘要翻译： 提供闪存器件，其包括垂直堆叠的多个层。 多个层中的每一个包括多个存储单元。 行解码器电耦合到多个层并且被配置为向多个层提供字线电压。 提供在多个层中的至少两层中的存储单元属于相同的存储块，并且与多个层中的至少两个层中的存储单元相关联的字线电耦合。

公开(公告)号：US07843733B2

公开(公告)日：2010-11-30

申请号：US12136933

申请日：2008-06-11

申请人： Doo-gon Kim ,  Ki-tae Park ,  Yeong-taek Lee

发明人： Doo-gon Kim ,  Ki-tae Park ,  Yeong-taek Lee

IPC分类号： G11C16/04

CPC分类号： G11C16/3418

摘要： Flash memory devices are provided including a plurality of layers stacked vertically. Each of the plurality of layers include a plurality of memory cells. A row decoder is electrically coupled to the plurality of layers and configured to supply a wordline voltage to the plurality of layers. Memory cells provided in at least two layers of the plurality of layers belong to a same memory block and wordlines associated with the memory cells in the at least two layers of the plurality of layers are electrically coupled.

摘要翻译： 提供闪存器件，其包括垂直堆叠的多个层。 多个层中的每一个包括多个存储单元。 行解码器电耦合到多个层并且被配置为向多个层提供字线电压。 提供在多个层中的至少两层中的存储单元属于相同的存储块，并且与多个层中的至少两个层中的存储单元相关联的字线电耦合。

公开(公告)号：US20090185422A1

公开(公告)日：2009-07-23

申请号：US12320003

申请日：2009-01-14

申请人： Myoung-gon Kang ,  Yeong-taek Lee ,  Ki-tae Park ,  Doo-gon Kim

发明人： Myoung-gon Kang ,  Yeong-taek Lee ,  Ki-tae Park ,  Doo-gon Kim

IPC分类号： G11C16/04 ,  G11C7/00 ,  G11C17/16 ,  G11C16/06

CPC分类号： G11C16/3418 ,  G11C7/02 ,  G11C8/10 ,  G11C16/0483 ,  G11C16/3427 ,  G11C17/16 ,  G11C29/52

摘要： A flash memory device includes first and second memory cell array blocks and a row decoder coupled to the first memory cell array block and the second. memory cell array block. The row decoder includes a block decoder, a single high voltage level shifter that is coupled to both the first and second memory cell array blocks, the single high voltage level shifter configured to provide a block wordline signal of a high voltage to the first and second memory array blocks in response to a block selection signal received from the block decoder, a first pass transistor unit, and a second pass transistor unit.

摘要翻译： 闪存器件包括第一和第二存储单元阵列块以及耦合到第一存储单元阵列块的行解码器和第二存储单元阵列块。 存储单元阵列块。 行解码器包括块解码器，耦合到第一和第二存储单元阵列块的单个高电压电平移位器，该单个高电压电平移位器被配置为向第一和第二存储单元阵列块提供高电压的块字线信号 存储器阵列块，响应于从块解码器接收的块选择信号，第一传输晶体管单元和第二传输晶体管单元。

公开(公告)号：US08411501B2

公开(公告)日：2013-04-02

申请号：US13372525

申请日：2012-02-14

申请人： Ki-tae Park ,  Yeong-taek Lee

发明人： Ki-tae Park ,  Yeong-taek Lee

IPC分类号： G11C11/34

CPC分类号： G11C16/3418

摘要： Provided is a method of programming a non-volatile memory device. The method includes applying a first programming pulse to a corresponding wordline of the non-volatile memory device, applying a second programming pulse to the wordline, wherein a voltage of the second programming pulse is different from that of the first programming pulse, and applying voltages to each bitline connected to the wordline, the voltages applied to each of the bitlines are different from each other according to a plurality of bit values to be programmed to corresponding memory cells in response to the first programming pulse or the second programming pulse.

摘要翻译： 提供了一种对非易失性存储器件进行编程的方法。 该方法包括将第一编程脉冲施加到非易失性存储器件的对应字线，向第二编程脉冲施加第二编程脉冲，其中第二编程脉冲的电压与第一编程脉冲的电压不同，并施加电压 对于连接到字线的每个位线，施加到每个位线的电压根据要响应于第一编程脉冲或第二编程脉冲被编程到相应存储器单元的多个位值而彼此不同。

公开(公告)号：US07911835B2

公开(公告)日：2011-03-22

申请号：US11859465

申请日：2007-09-21

申请人： Doo-gon Kim ,  Ki-tae Park ,  Yeong-taek Lee

发明人： Doo-gon Kim ,  Ki-tae Park ,  Yeong-taek Lee

IPC分类号： G11C16/04

CPC分类号： G11C16/10 ,  G11C11/5628

摘要： Non-volatile memory devices and methods of programming the non-volatile memory devices use six threshold voltage levels. Data also may be read from the non-volatile memory devices. The non-volatile memory devices include a first non-volatile memory cell and a second non-volatile memory cell, each of which can be programmed with first through sixth threshold voltage levels that sequentially increase. Programming includes first, second and third data bit program operations. In the first and second data bit program operation, the first and second non-volatile memory cells are programmed with the first or second threshold voltage level in order to store first and second bits of data. In the third data bit program operation, the first non-volatile memory cell is programmed with the third or fourth threshold voltage level according to the first and second bits of the data in order to store a third bit of the data. Fourth and fifth data bit program operations also may be provided.

摘要翻译： 非易失性存储器件和非易失性存储器件的编程方法使用六个阈值电压电平。 也可以从非易失性存储器件读取数据。 非易失性存储器件包括第一非易失性存储器单元和第二非易失性存储器单元，其中每一个都可以用顺序增加的第一至第六阈值电压电平进行编程。 编程包括第一，第二和第三数据位程序操作。 在第一和第二数据位编程操作中，第一和第二非易失性存储单元用第一或第二阈值电压电平进行编程，以便存储第一和第二位数据。 在第三数据比特编程操作中，根据数据的第一和第二比特，第一非易失性存储单元用第三或第四阈值电压电平进行编程，以便存储数据的第三位。 也可以提供第四和第五数据位程序操作。

公开(公告)号：US20080084740A1

公开(公告)日：2008-04-10

申请号：US11859465

申请日：2007-09-21

申请人： Doo-gon Kim ,  Ki-tae Park ,  Yeong-taek Lee

发明人： Doo-gon Kim ,  Ki-tae Park ,  Yeong-taek Lee

IPC分类号： G11C16/10

CPC分类号： G11C16/10 ,  G11C11/5628

摘要： Non-volatile memory devices and methods of programming the non-volatile memory devices use six threshold voltage levels. Data also may be read from the non-volatile memory devices. The non-volatile memory devices include a first non-volatile memory cell and a second non-volatile memory cell, each of which can be programmed with first through sixth threshold voltage levels that sequentially increase. Programming includes first, second and third data bit program operations. In the first and second data bit program operation, the first and second non-volatile memory cells are programmed with the first or second threshold voltage level in order to store first and second bits of data. In the third data bit program operation, the first non-volatile memory cell is programmed with the third or fourth threshold voltage level according to the first and second bits of the data in order to store a third bit of the data. Fourth and fifth data bit program operations also may be provided.

摘要翻译： 非易失性存储器件和非易失性存储器件的编程方法使用六个阈值电压电平。 也可以从非易失性存储器件读取数据。 非易失性存储器件包括第一非易失性存储器单元和第二非易失性存储器单元，其中每一个都可以用顺序增加的第一至第六阈值电压电平进行编程。 编程包括第一，第二和第三数据位程序操作。 在第一和第二数据位编程操作中，第一和第二非易失性存储单元用第一或第二阈值电压电平进行编程，以便存储第一和第二位数据。 在第三数据比特编程操作中，根据数据的第一和第二比特，第一非易失性存储单元用第三或第四阈值电压电平进行编程，以便存储数据的第三位。 也可以提供第四和第五数据位程序操作。