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1.发明授权公开(公告)号：US07718502B2
公开(公告)日：2010-05-18
申请号：US11984167
申请日：2007-11-14
IPC分类号： H01L29/72
CPC分类号： H01C17/075 , H01C7/006 , H01L23/5228 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor apparatus includes a wiring pattern, an insulating film, and a thin-metal-film resistor element. The insulating film is formed on the wiring pattern having connection holes vertically penetrating there-through to expose part of the wiring pattern at bottom regions of the connection holes. The connection holes are arranged with a space there-between. The thin-metal-film resistor element is formed on the insulating film and extending to continuously overlay and contact surfaces of the insulating film, inner walls of the connection holes, and the wiring pattern at the bottom regions of the connection holes.
摘要翻译： 半导体装置包括布线图案，绝缘膜和薄金属膜电阻元件。 绝缘膜形成在具有垂直贯穿其中的连接孔的布线图案上，以暴露连接孔的底部区域的布线图案的一部分。 连接孔之间具有空间。 金属薄膜电阻元件形成在绝缘膜上并延伸到绝缘膜，连接孔的内壁和连接孔的底部区域的布线图案的连续覆盖和接触。
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公开(公告)号：US20060027892A1
公开(公告)日：2006-02-09
申请号：US11060753
申请日：2005-08-16
IPC分类号： H01L29/00
CPC分类号： H01L23/5228 , H01L21/76805 , H01L21/76843 , H01L27/0802 , H01L28/24 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device equipped with a metal thin film resistor is disclosed. The semiconductor device includes a second interlayer insulating film formed on a first interlayer insulating film including a formation area of a wiring pattern. Connecting holes are formed in the second interlayer insulating film corresponding to both ends of the metal thin film resistor and the wiring pattern. An upper part of each connecting hole is formed in a taper shape. A sidewall is formed on the inner wall of each connecting hole. The metal thin film resistor is formed on the second interlayer insulating film between the connecting holes, inside of each connecting hole, and on the wiring pattern.
摘要翻译： 公开了一种配备有金属薄膜电阻器的半导体器件。 半导体器件包括形成在包括布线图案的形成区域的第一层间绝缘膜上的第二层间绝缘膜。 在与金属薄膜电阻器的两端对应的第二层间绝缘膜和布线图案中形成连接孔。 每个连接孔的上部形成为锥形。 在每个连接孔的内壁上形成侧壁。 金属薄膜电阻器形成在第二层间绝缘膜之间的连接孔之间，每个连接孔内部和布线图案之间。
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3.发明授权公开(公告)号：US07202549B2
公开(公告)日：2007-04-10
申请号：US10848384
申请日：2004-05-19
IPC分类号： H01L29/00
CPC分类号： H01L28/20 , H01L27/0611 , H01L27/0802
摘要： A semiconductor device, a method for manufacturing the semiconductor device, and an integrated circuit including the semiconductor device are disclosed. The semiconductor device includes a substrate section, a resistor formed on the substrate section, a metal pattern formed on the resistor, an oxide pattern formed on the metal pattern, and a protective film covering the resistor, the metal pattern and the oxide pattern. With this structure, the metal pattern sufficiently prevents formation of an oxide film on a surface of the resistor even when dry ashing or dry etching is performed in the manufacturing process.
摘要翻译： 公开了半导体器件，半导体器件的制造方法和包括半导体器件的集成电路。 该半导体装置包括基板部，形成在基板部上的电阻，形成在电阻上的金属图案，形成在金属图案上的氧化物图案，以及覆盖电阻，金属图案和氧化物图案的保护膜。 通过这种结构，即使在制造过程中进行干法灰化或干法蚀刻，金属图案也充分地防止了在电阻器的表面上形成氧化膜。
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公开(公告)号：US20050212085A1
公开(公告)日：2005-09-29
申请号：US11059725
申请日：2005-02-17
IPC分类号： H01L21/3205 , H01L21/02 , H01L21/822 , H01L23/52 , H01L23/522 , H01L23/525 , H01L27/01 , H01L27/04 , H01L29/00
CPC分类号： H01L27/0802 , H01L23/5228 , H01L27/016 , H01L28/24 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device includes: an insulating film; a metal thin-film resistance element; a wiring pattern formed on the insulating film, a part of which forms an electrode for electrically connecting with the metal thin-film resistance element; and a side wall produced at least on a side surface of the electrode of the wiring pattern, and made of an insulation material, wherein: the metal thin-film resistance element is produced across a top surface of the electrode and a surface of the insulating film via a surface of the side wall.
摘要翻译： 半导体器件包括：绝缘膜; 金属薄膜电阻元件; 形成在所述绝缘膜上的布线图形，其一部分形成用于与所述金属薄膜电阻元件电连接的电极; 以及至少在所述布线图案的电极的侧面上形成的侧壁，并且由绝缘材料制成，其中：所述金属薄膜电阻元件跨越所述电极的顶表面和所述绝缘体的表面 膜通过侧壁的表面。
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5.发明申请公开(公告)号：US20080090371A1
公开(公告)日：2008-04-17
申请号：US11984167
申请日：2007-11-14
IPC分类号： H01L21/20
CPC分类号： H01C17/075 , H01C7/006 , H01L23/5228 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor apparatus includes a wiring pattern, an insulating film, and a thin-metal-film resistor element. The insulating film is formed on the wiring pattern having connection holes vertically penetrating there-through to expose part of the wiring pattern at bottom regions of the connection holes. The connection holes are arranged with a space there-between. The thin-metal-film resistor element is formed on the insulating film and extending to continuously overlay and contact surfaces of the insulating film, inner walls of the connection holes, and the wiring pattern at the bottom regions of the connection holes.
摘要翻译： 半导体装置包括布线图案，绝缘膜和薄金属膜电阻元件。 绝缘膜形成在具有垂直贯穿其中的连接孔的布线图案上，以暴露连接孔的底部区域的布线图案的一部分。 连接孔之间具有空间。 金属薄膜电阻元件形成在绝缘膜上并延伸到绝缘膜，连接孔的内壁和连接孔的底部区域的布线图案的连续覆盖和接触。
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公开(公告)号：US20080100348A1
公开(公告)日：2008-05-01
申请号：US11792471
申请日：2006-09-21
CPC分类号： H01L27/016 , H01L23/5228 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device, includes a lower layer side insulation film; a wiring pattern formed on the lower layer side insulation film; a base insulation film formed on the lower layer side insulation film and the wiring pattern; and a plurality of metal thin film resistance elements formed on the base insulation film; wherein a connection hole is formed in the base insulation film on the wiring pattern; the wiring pattern and the metal thin film resistance element are electrically connected in the connection hole; the metal thin film resistance element has a belt shape part arranged separately from the connection hole and a connection part continuously formed with the belt shape part and connected to the wiring pattern in the connection hole; and the connection parts of at least two of the metal thin film resistance element are formed in the single connection hole with a gap in between said connection parts.
摘要翻译： 一种半导体器件，包括下层侧绝缘膜; 形成在下层侧绝缘膜上的布线图案; 形成在下层侧绝缘膜和布线图案上的基底绝缘膜; 以及形成在所述基底绝缘膜上的多个金属薄膜电阻元件; 其中在所述布线图案上的所述基底绝缘膜中形成连接孔; 布线图案和金属薄膜电阻元件在连接孔中电连接; 金属薄膜电阻元件具有与连接孔分开布置的带状部分和连续形成带状部分并且连接到连接孔中的布线图案的连接部分; 并且金属薄膜电阻元件中的至少两个的连接部分形成在单个连接孔中，在所述连接部分之间具有间隙。
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7.发明授权公开(公告)号：US07312515B2
公开(公告)日：2007-12-25
申请号：US10861931
申请日：2004-06-07
IPC分类号： H01L29/72
CPC分类号： H01C17/075 , H01C7/006 , H01L23/5228 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor apparatus includes a wiring pattern, an insulating film, and a thin-metal-film resistor element. The insulating film is formed on the wiring pattern having connection holes vertically penetrating there-through to expose part of the wiring pattern at bottom regions of the connection holes. The connection holes are arranged with a space there-between. The thin-metal-film resistor element is formed on the insulating film and extending to continuously overlay and contact surfaces of the insulating film, inner walls of the connection holes, and the wiring pattern at the bottom regions of the connection holes.
摘要翻译： 半导体装置包括布线图案，绝缘膜和薄金属膜电阻元件。 绝缘膜形成在具有垂直贯穿其中的连接孔的布线图案上，以暴露连接孔的底部区域的布线图案的一部分。 连接孔之间具有空间。 金属薄膜电阻元件形成在绝缘膜上并延伸到绝缘膜，连接孔的内壁和连接孔的底部区域的布线图案的连续覆盖和接触。
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公开(公告)号：US07999352B2
公开(公告)日：2011-08-16
申请号：US11060753
申请日：2005-02-18
IPC分类号： H01L27/08
CPC分类号： H01L23/5228 , H01L21/76805 , H01L21/76843 , H01L27/0802 , H01L28/24 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device equipped with a metal thin film resistor is disclosed. The semiconductor device includes a second interlayer insulating film formed on a first interlayer insulating film including a formation area of a wiring pattern. Connecting holes are formed in the second interlayer insulating film corresponding to both ends of the metal thin film resistor and the wiring pattern. An upper part of each connecting hole is formed in a taper shape. A sidewall is formed on the inner wall of each connecting hole. The metal thin film resistor is formed on the second interlayer insulating film between the connecting holes, inside of each connecting hole, and on the wiring pattern.
摘要翻译： 公开了一种配备有金属薄膜电阻器的半导体器件。 半导体器件包括形成在包括布线图案的形成区域的第一层间绝缘膜上的第二层间绝缘膜。 在与金属薄膜电阻器的两端对应的第二层间绝缘膜和布线图案中形成连接孔。 每个连接孔的上部形成为锥形。 在每个连接孔的内壁上形成侧壁。 金属薄膜电阻器形成在第二层间绝缘膜之间的连接孔之间，每个连接孔内部和布线图案之间。
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公开(公告)号：US07986028B2
公开(公告)日：2011-07-26
申请号：US11792471
申请日：2006-09-21
IPC分类号： H01L29/00
CPC分类号： H01L27/016 , H01L23/5228 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device, includes a lower layer side insulation film; a wiring pattern formed on the lower layer side insulation film; a base insulation film formed on the lower layer side insulation film and the wiring pattern; and a plurality of metal thin film resistance elements formed on the base insulation film; wherein a connection hole is formed in the base insulation film on the wiring pattern; the wiring pattern and the metal thin film resistance element are electrically connected in the connection hole; the metal thin film resistance element has a belt shape part arranged separately from the connection hole and a connection part continuously formed with the belt shape part and connected to the wiring pattern in the connection hole; and the connection parts of at least two of the metal thin film resistance element are formed in the single connection hole with a gap in between said connection parts.
摘要翻译： 一种半导体器件，包括下层侧绝缘膜; 形成在下层侧绝缘膜上的布线图案; 形成在下层侧绝缘膜和布线图案上的基底绝缘膜; 以及形成在所述基底绝缘膜上的多个金属薄膜电阻元件; 其中在所述布线图案上的所述基底绝缘膜中形成连接孔; 布线图案和金属薄膜电阻元件在连接孔中电连接; 金属薄膜电阻元件具有与连接孔分开布置的带状部分和连续形成带状部分并且连接到连接孔中的布线图案的连接部分; 并且金属薄膜电阻元件中的至少两个的连接部分形成在单个连接孔中，在所述连接部分之间具有间隙。
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公开(公告)号：US5351137A
公开(公告)日：1994-09-27
申请号：US159206
申请日：1993-11-30
申请人： Masami Kato , Takao Kato , Yasunori Hashimoto
发明人： Masami Kato , Takao Kato , Yasunori Hashimoto
CPC分类号： H04N1/40075 , H04N1/40062 , H04N1/40068 , H04N1/4052
摘要： In a pixel density converting apparatus according to the present invention, a pixel density conversion element for converting a pixel density by a factor of an arbitrary value, such as an element of the projection method or the linear interpolation method, a pixel density conversion element for increasing or decreasing a pixel density by a factor of an integer, such as an element of the majority or logical OR method, and a binarization element for conducting binarization while correcting quantizing errors, such as an element of the error diffusion method or the average error minimizing method, are combined with each other with the advantages and disadvantages of the respective elements taken into consideration, so as to achieve excellent conversion whether or not the image on which pixel density conversion is conducted or an image area is a pseudo half-tone processed image. In consequence, excellent pixel density conversion is achieved on a binary image in which a pseudo half-tone processed image and characters or line drawings are present in a mixed state.
摘要翻译： 在根据本发明的像素密度转换装置中，像素密度转换元件用于将诸如投影方法的元素或线性内插法的任意值的像素密度的像素密度转换成像素密度转换元件， 增加或减少像素密度乘以整数因子，例如大多数或逻辑OR方法的元素，以及用于在校正量化误差的同时进行二值化的二值化元素，例如误差扩散方法的元素或平均误差 最小化方法相互结合，考虑到各个元件的优点和缺点，以便无论进行像素密度转换的图像还是图像区域都是伪半色调处理，实现优异的转换 图片。 因此，在混合状态下存在伪半色调处理的图像和字符或线图的二进制图像上实现了优异的像素密度转换。
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