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公开(公告)号：US11271152B2
公开(公告)日：2022-03-08
申请号：US16875259
申请日：2020-05-15
申请人： KIOXIA CORPORATION
发明人： Kenichi Murooka
摘要： A semiconductor memory device according to an embodiment comprises a memory cell array configured from a plurality of row lines and column lines that intersect one another, and from a plurality of memory cells disposed at each of intersections of the row lines and column lines and each including a variable resistance element. Where a number of the row lines is assumed to be N, a number of the column lines is assumed to be M, and a ratio of a cell current flowing in the one of the memory cells when a voltage that is half of the select voltage is applied to the one of the memory cells to a cell current flowing in the one of the memory cells when the select voltage is applied to the one of the memory cells is assumed to be k, a relationship M2
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公开(公告)号：US11800825B2
公开(公告)日：2023-10-24
申请号：US17584868
申请日：2022-01-26
申请人： Kioxia Corporation
发明人： Kenichi Murooka
CPC分类号： H10N70/826 , G11C8/10 , G11C13/0002 , G11C13/0023 , H10B63/80 , H10B63/845 , H10N70/021 , H10N70/20 , H10N70/823 , H10N70/8833 , H10N70/8836 , H10N70/8845 , G11C2213/71 , G11C2213/72
摘要： A semiconductor memory device according to an embodiment comprises a memory cell array configured from a plurality of row lines and column lines that intersect one another, and from a plurality of memory cells disposed at each of intersections of the row lines and column lines and each including a variable resistance element. Where a number of the row lines is assumed to be N, a number of the column lines is assumed to be M, and a ratio of a cell current flowing in the one of the memory cells when a voltage that is half of the select voltage is applied to the one of the memory cells to a cell current flowing in the one of the memory cells when the select voltage is applied to the one of the memory cells is assumed to be k, a relationship M2
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