公开(公告)号：US20240276721A1

公开(公告)日：2024-08-15

申请号：US18439898

申请日：2024-02-13

Applicant: Kioxia Corporation

Inventor： Kohei DATE ,  Kenji AOYAMA ,  Keisuke SUDA ,  Minami TANAKA ,  Satoshi NAGASHIMA

IPC: H10B43/27 ,  H10B43/10

CPC classification number: H10B43/27 ,  H10B43/10

Abstract: According to one embodiment, a semiconductor memory device includes a plurality of conductor layers including a first conductor layer as an uppermost layer; a plurality of memory pillars penetrating the conductor layers; and a member that includes a first portion extending in the conductor layers and a plurality of second portions RT provided apart from each other on the uppermost layer side of the conductor layers, and divides the conductor layers in a direction in a substrate surface; wherein a lower surface of the second portion is located below an upper surface of the first conductor layer, and an upper surface of the second portion is wider in a width in the direction, than the lower surface of the second portion and than the first portion.

公开(公告)号：US20240096416A1

公开(公告)日：2024-03-21

申请号：US18335680

申请日：2023-06-15

Applicant: Kioxia Corporation

Inventor： Kohei DATE ,  Keisuke SUDA

IPC: G11C16/04 ,  H01L23/528 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35

CPC classification number: G11C16/0483 ,  H01L23/5283 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35

Abstract: According to one embodiment, a semiconductor memory device includes: stacked interconnects including a first interconnect layer and a second interconnect layer, the first interconnect layer including a first area and a second area arranged in a first direction, the second interconnect layer being arranged above the first interconnect layer in a second direction intersecting the first direction, the second interconnect layer not including the first area and including the second area; a first memory pillar arranged in the first area and passing through the first interconnect layer in the second direction; and a second memory pillar arranged in the second area and passing through the first interconnect layer and the second interconnect layer in the second direction.