公开(公告)号：US20230307050A1

公开(公告)日：2023-09-28

申请号：US17943487

申请日：2022-09-13

Applicant: Kioxia Corporation

Inventor： Keisuke SUDA ,  Ryota SUZUKI ,  Kenta YAMADA

IPC: G11C16/04 ,  G11C5/02 ,  G11C16/26 ,  G11C16/34 ,  G11C16/14 ,  H01L27/11519 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/11582

CPC classification number: G11C16/0483 ,  G11C5/025 ,  G11C16/26 ,  G11C16/3436 ,  G11C16/14 ,  H01L27/11519 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/11582

Abstract: A semiconductor memory device includes memory blocks arranged in a first direction and bit lines that are arranged in a second direction, and are arranged with the memory blocks in a third direction. The memory block includes first conductive layers arranged in the third direction, a second conductive layer disposed on a side opposite to the bit lines in the third direction with respect to the first conductive layers, semiconductor layers that extend in the third direction, are opposed to the first conductive layers, have one ends in the third direction electrically connected to the second conductive layer, and have the other ends in the third direction electrically connected to the bit lines, and electric charge accumulating films disposed between the first conductive layers and the semiconductor layers. The first conductive layers and the second conductive layer are separated between the memory blocks.

公开(公告)号：US20240389328A1

公开(公告)日：2024-11-21

申请号：US18664450

申请日：2024-05-15

Applicant: Kioxia Corporation

Inventor： Kazuma HAYASHI ,  Shinya ARAI ,  Keisuke SUDA ,  Masakazu SAWANO

IPC: H10B43/35 ,  H01L23/528 ,  H10B43/10

Abstract: In general, according to one embodiment, a semiconductor device includes: a plurality of first conductor layers arranged apart from each other in a first direction; a memory pillar extending in the first direction and including a portion crossing a respective one of the first conductor layers, the portion functioning as a memory cell; and a first conductor member surrounding, in a first direction perspective, the first conductor layers and the memory pillar, the first conductor member crossing an extension of at least one of the first conductor layers. The first conductor member includes a first direction first end having, in the first direction perspective, a dent and rise profile in a longitudinal direction of the first conductor member.

公开(公告)号：US20240276721A1

公开(公告)日：2024-08-15

申请号：US18439898

申请日：2024-02-13

Applicant: Kioxia Corporation

Inventor： Kohei DATE ,  Kenji AOYAMA ,  Keisuke SUDA ,  Minami TANAKA ,  Satoshi NAGASHIMA

IPC: H10B43/27 ,  H10B43/10

CPC classification number: H10B43/27 ,  H10B43/10

Abstract: According to one embodiment, a semiconductor memory device includes a plurality of conductor layers including a first conductor layer as an uppermost layer; a plurality of memory pillars penetrating the conductor layers; and a member that includes a first portion extending in the conductor layers and a plurality of second portions RT provided apart from each other on the uppermost layer side of the conductor layers, and divides the conductor layers in a direction in a substrate surface; wherein a lower surface of the second portion is located below an upper surface of the first conductor layer, and an upper surface of the second portion is wider in a width in the direction, than the lower surface of the second portion and than the first portion.

公开(公告)号：US20240096416A1

公开(公告)日：2024-03-21

申请号：US18335680

申请日：2023-06-15

Applicant: Kioxia Corporation

Inventor： Kohei DATE ,  Keisuke SUDA

IPC: G11C16/04 ,  H01L23/528 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35

CPC classification number: G11C16/0483 ,  H01L23/5283 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35

Abstract: According to one embodiment, a semiconductor memory device includes: stacked interconnects including a first interconnect layer and a second interconnect layer, the first interconnect layer including a first area and a second area arranged in a first direction, the second interconnect layer being arranged above the first interconnect layer in a second direction intersecting the first direction, the second interconnect layer not including the first area and including the second area; a first memory pillar arranged in the first area and passing through the first interconnect layer in the second direction; and a second memory pillar arranged in the second area and passing through the first interconnect layer and the second interconnect layer in the second direction.

公开(公告)号：US20230086773A1

公开(公告)日：2023-03-23

申请号：US17693617

申请日：2022-03-14

Applicant: Kioxia Corporation

Inventor： Akira YOTSUMOTO ,  Keisuke SUDA ,  Kenji TASHIRO ,  Tetsuya YAMASHITA ,  Daigo ICHINOSE

IPC: H01L27/11565 ,  H01L27/11582

Abstract: According to one embodiment, a semiconductor memory device includes: a stacked body having a stacked structure in which a plurality of conductive layers and a plurality of insulating layers are alternately stacked one by one, the stacked body including a memory region and a dummy region arranged in a first direction intersecting a stacking direction of the plurality of conductive layers, the dummy region including a first stepped portion in which at least a part of the plurality of conductive layers on an upper layer side is processed in a stepped shape and terminates at an end portion opposite to the memory region in the first direction; and first and second plate-like portions extending in the stacking direction and the first direction in the stacked body at positions in the memory region away from each other in a second direction intersecting the stacking direction and the first direction, the first and second plate-like portions being directly or indirectly connected to each other and terminating in the dummy region, each of the first and second plate-like portions dividing the stacked body excluding at least a part of the end portion of the dummy region in the second direction.

公开(公告)号：US20230276626A1

公开(公告)日：2023-08-31

申请号：US17898944

申请日：2022-08-30

Applicant: Kioxia Corporation

Inventor： Hideto TAKEKIDA ,  Keisuke SUDA ,  Naoyuki IIDA ,  Kohei NYUI ,  Ryo HIKIDA

IPC: H01L27/11582 ,  H01L27/11519 ,  H01L27/11565 ,  H01L27/11556 ,  H01L23/528

CPC classification number: H01L27/11582 ,  H01L27/11519 ,  H01L27/11565 ,  H01L27/11556 ,  H01L23/5283

Abstract: A semiconductor storage device includes: a first semiconductor layer through first conductive layers; a gate insulating film between the first conductive layers and the first semiconductor layer; a first structure facing the first conductive layers; a second semiconductor layer connected to the first semiconductor layer and the first structure; a third semiconductor layer between the second semiconductor layer and the first conductive layers; a fourth semiconductor layer including a first portion along a bottom surface of the third semiconductor layer and a second portion along a top surface of the second semiconductor layer; and a first insulating layer, between the first and second portions, including a first region spaced from the first structure with a distance longer than a first distance that contains a nitride film, and a second region spaced from the first structure with a distance shorter than the first distance that does not contain nitrogen.

公开(公告)号：US20230262983A1

公开(公告)日：2023-08-17

申请号：US17931621

申请日：2022-09-13

Applicant: Kioxia Corporation

Inventor： Hisashi HARADA ,  Keisuke SUDA

IPC: H01L27/1157 ,  G11C5/06 ,  H01L27/11578

CPC classification number: H01L27/1157 ,  G11C5/063 ,  H01L27/11578

Abstract: According to one embodiment, a semiconductor memory device includes: a semiconductor layer arranged above a substrate in a first direction; a first interconnect layer between the substrate and the semiconductor layer; a second interconnect layer arranged adjacent to the first interconnect layer in a second direction; a plurality of memory pillars; and a first member between the first interconnect layer and the second interconnect layer. The semiconductor layer has, on a side of a second surface facing a first surface in contact with the first member, a first projecting portion projecting in the first direction and overlapping a part of an area in the first direction, the area being provided with the first interconnect layer and the first member.