公开(公告)号：US20230317181A1

公开(公告)日：2023-10-05

申请号：US17902754

申请日：2022-09-02

Applicant: Kioxia Corporation

Inventor： Kenro KIKUCHI ,  Masahiko IGA ,  Nobushi MATSUURA

IPC: G11C16/34 ,  G11C16/24 ,  G11C16/16 ,  G11C16/08

CPC classification number: G11C16/3445 ,  G11C16/08 ,  G11C16/16 ,  G11C16/24

Abstract: A semiconductor storage device of embodiments includes a block constituted with a plurality of strings each including a plurality of memory cell transistors, a plurality of word lines, a bit line, a source line, and a control circuit configured to perform erase operation on the plurality of memory cell transistors, and the control circuit changes setting of first erase-verify operation included in the erase operation for an open block including a memory cell transistor having an erase level and setting of second erase-verify operation included in erase operation for a closed block not including a memory cell transistor having an erase block.

公开(公告)号：US20230064140A1

公开(公告)日：2023-03-02

申请号：US17686835

申请日：2022-03-04

Applicant: Kioxia Corporation

Inventor： Yasuhiro SHIINO ,  Masahiko IGA ,  Shinji SUZUKI

IPC: G11C16/34 ,  G11C16/10 ,  G11C16/26 ,  G11C7/08 ,  G11C7/10

Abstract: A second conductor, third conductor, and fourth conductor sandwiches a first layer together with a first semiconductor. The fourth conductor is positioned farther from the first conductor than the third conductor, which is positioned farther from first conductor than the second conductor. A first circuit is configured to apply a first potential to the first and second conductors, apply a second potential lower than the first potential to the third conductor in parallel with the application of the first potential, and apply a third potential higher than the second potential and lower than the first potential to the fourth conductor in parallel with the application of the first potential.

公开(公告)号：US20230307060A1

公开(公告)日：2023-09-28

申请号：US17930625

申请日：2022-09-08

Applicant: Kioxia Corporation

Inventor： Masahiko IGA ,  Kenro KIKUCHI ,  Nobushi MATSUURA

IPC: G11C16/14 ,  G11C16/34 ,  G11C16/26

CPC classification number: G11C16/14 ,  G11C16/3459 ,  G11C16/26 ,  G11C16/3445 ,  G11C16/0483

Abstract: A semiconductor memory device performs a write operation and an erase operation. The write operation includes a first program operation that applies a first program voltage to a first conductive layer. The first program voltage increases by a first offset voltage together with an increase in an execution count of a first write loop. An erase operation includes a program voltage control operation and an erase voltage supply operation that applies an erase voltage to a first wiring. The program voltage control operation includes a second program operation that applies a second program voltage to a third conductive layer. The second program voltage increases by a second offset voltage together with an increase in a number of times of execution of a second write loop. A magnitude of the first program voltage is adjusted according to a magnitude of the second program voltage.