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    NONVOLATILE SEMICONDUCTOR MEMORY DEVICE
    2.
    发明申请
    NONVOLATILE SEMICONDUCTOR MEMORY DEVICE 有权

    公开(公告)号：US20220262439A1

    公开(公告)日：2022-08-18

    申请号：US17734359

    申请日：2022-05-02

    Applicant: KIOXIA CORPORATION

    Inventor： Yasuhiro SHIINO ,  Eietsu TAKAHASHI

    IPC: G11C16/04 ,  G11C11/56 ,  G11C16/16 ,  G11C16/34 ,  G11C16/10 ,  G11C16/14 ,  G11C16/08 ,  G11C16/28

    Abstract: A nonvolatile semiconductor memory device includes a control circuit configured to control a soft program operation of setting nonvolatile memory cells to a first threshold voltage distribution state of the nonvolatile memory cells. When a characteristic of the nonvolatile memory cells is in a first state, the control circuit executes the soft program operation by applying a first voltage for setting the nonvolatile memory cells to the first threshold voltage distribution state to first word lines, and applying a second voltage higher than the first voltage to a second word line. When the characteristic of the nonvolatile memory cells is in a second state, the control circuit executes the soft program operation by applying a third voltage equal to or lower than the first voltage to the first word lines and applying a fourth voltage lower than the second voltage to the second word line.

    SEMICONDUCTOR STORAGE DEVICE
    4.
    发明公开
    SEMICONDUCTOR STORAGE DEVICE 审中-公开

    公开(公告)号：US20240087659A1

    公开(公告)日：2024-03-14

    申请号：US18163846

    申请日：2023-02-02

    Applicant: Kioxia Corporation

    Inventor： Ryota HIRAI ,  Yasuhiro SHIINO

    IPC: G11C16/34 ,  G11C16/10 ,  G11C16/16

    CPC classification number: G11C16/3495 ,  G11C16/10 ,  G11C16/16 ,  G11C16/3459

    Abstract: A semiconductor storage device that is capable of improving reliability includes: a non-volatile memory provided with a block including a plurality of memory cell transistors connected to a word line; and a controller configured to monitor a threshold voltage distribution width of the plurality of memory cell transistors after performing at least one of an erasing operation on the block and a preliminary write operation on the plurality of memory cell transistors and to classify the plurality of memory cell transistors according to the threshold voltage distribution width of the plurality of memory cell transistors.

    SEMICONDUCTOR MEMORY DEVICE
    5.
    发明申请
    SEMICONDUCTOR MEMORY DEVICE 有权

    公开(公告)号：US20230056364A1

    公开(公告)日：2023-02-23

    申请号：US17654136

    申请日：2022-03-09

    Applicant: KIOXIA CORPORATION

    Inventor： Manabu SAKANIWA ,  Yasuhiro SHIINO ,  Kota NISHIKAWA ,  Yu ISHIYAMA ,  Shinji SUZUKI

    IPC: G11C16/16 ,  H01L27/11556 ,  H01L27/11582 ,  G11C16/04

    Abstract: A semiconductor memory device includes a substrate, gate electrodes, a semiconductor layer opposed to gate electrodes, an electric charge accumulating layer disposed between gate electrodes and the semiconductor layer, a conductive layer connected to one end portion of the semiconductor layer, and a control circuit electrically connected to gate electrodes and the conductive layer. Gate electrodes include first gate electrodes, second gate electrodes, and third gate electrode. The control circuit is configured to perform an erase operation. The erase operation includes: at least one-time first operation that applies a first voltage to the conductive layer; a second operation performed after the first operation, the second operation applying a second voltage to the third gate electrode; and at least one-time third operation performed after the second operation, the third operation applying a third voltage same as or larger than the first voltage to the conductive layer.

    SEMICONDUCTOR MEMORY DEVICE
    6.
    发明公开
    SEMICONDUCTOR MEMORY DEVICE 审中-公开

    公开(公告)号：US20240079065A1

    公开(公告)日：2024-03-07

    申请号：US18446106

    申请日：2023-08-08

    Applicant: Kioxia Corporation

    Inventor： Yasuhiro SHIINO ,  Kenrou KIKUCHI

    IPC: G11C16/10 ,  G11C16/08 ,  G11C16/16 ,  G11C16/26

    CPC classification number: G11C16/102 ,  G11C16/08 ,  G11C16/16 ,  G11C16/26

    Abstract: According to one embodiment, a semiconductor memory device includes a first memory sub-block and a second memory sub-block arranged in a first direction and a control circuit. The first memory sub-block includes a first memory cell and a first word line connected to the first memory cell. The second memory sub-block includes a second memory cell and a second word line connected to the second memory cell. The control circuit executes a first and a second write operation on the first memory cell. In the first write operation, the control circuit applies a program voltage to the first word line and a first unselect write voltage to the second word line. In the second write operation, the program voltage is applied to the first word line and a second unselect write voltage is applied to the second word line.

    MEMORY DEVICE AND MEMORY SYSTEM
    7.
    发明申请
    MEMORY DEVICE AND MEMORY SYSTEM 有权

    公开(公告)号：US20230064140A1

    公开(公告)日：2023-03-02

    申请号：US17686835

    申请日：2022-03-04

    Applicant: Kioxia Corporation

    Inventor： Yasuhiro SHIINO ,  Masahiko IGA ,  Shinji SUZUKI

    IPC: G11C16/34 ,  G11C16/10 ,  G11C16/26 ,  G11C7/08 ,  G11C7/10

    Abstract: A second conductor, third conductor, and fourth conductor sandwiches a first layer together with a first semiconductor. The fourth conductor is positioned farther from the first conductor than the third conductor, which is positioned farther from first conductor than the second conductor. A first circuit is configured to apply a first potential to the first and second conductors, apply a second potential lower than the first potential to the third conductor in parallel with the application of the first potential, and apply a third potential higher than the second potential and lower than the first potential to the fourth conductor in parallel with the application of the first potential.

    SEMICONDUCTOR STORAGE DEVICE
    10.
    发明申请
    SEMICONDUCTOR STORAGE DEVICE 有权

    公开(公告)号：US20220262444A1

    公开(公告)日：2022-08-18

    申请号：US17463693

    申请日：2021-09-01

    Applicant: Kioxia Corporation

    Inventor： Ryota HIRAI ,  Daisuke ARIZONO ,  Yasuhiro SHIINO ,  Takuya KUSAKA

    IPC: G11C16/34 ,  G11C16/08 ,  G11C16/26 ,  G11C16/30 ,  G11C16/04 ,  G11C16/32

    Abstract: A non-volatile memory of an embodiment includes: a memory cell array including a plurality of memory cell transistors; a plurality of word lines connected to a plurality of gates of the plurality of respective memory cell transistors; a VPGM monitor connected to at least one of the plurality of word lines; and a sequencer. When writing voltage is applied to a selected word line selected from among the plurality of word lines at data writing to the memory cell array, the sequencer detects voltage of the selected word line through the VPGM monitor and determines whether detected voltage obtained through the detection has reached a predetermined value.

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