公开(公告)号：US20230317155A1

公开(公告)日：2023-10-05

申请号：US17943432

申请日：2022-09-13

Applicant: Kioxia Corporation

Inventor： Ryousuke TAKIZAWA

IPC: G11C13/00

CPC classification number: G11C13/004 ,  G11C13/0038 ,  G11C13/0069

Abstract: A first switching element in a memory cell is configured to transition from an ON state to an OFF state in response to a voltage applied between its two terminals being decreased. A read circuit is configured to place the second interconnect in a floating state, and, after placing the second interconnect in the floating state and based on a comparison between a first voltage of the second interconnect at a time point of the first switching element becoming the OFF state and a second voltage, either apply a third voltage to the second interconnect and then place the second interconnect in the floating state, or apply a fourth voltage lower than the third voltage to the second interconnect without applying the third voltage to the second interconnect.

公开(公告)号：US20220406374A1

公开(公告)日：2022-12-22

申请号：US17549337

申请日：2021-12-13

Applicant: Kioxia Corporation

Inventor： Masahiro TAKAHASHI ,  Hiroshi ITO ,  Ryousuke TAKIZAWA

IPC: G11C13/00 ,  G11C5/06

Abstract: According to one embodiment, a memory device includes a first wiring line, a second wiring line, a memory cell connected between the first and second wiring lines, including a resistance change memory element having first and second resistance states, and a two-terminal switching element connected in series to the resistance change memory element, and a voltage application circuit which applies a write voltage signal having a first polarity and setting a desired resistance state to the resistance change memory element, to the memory cell, and applies, after the write voltage signal is applied to the memory cell, a second polarity voltage signal having a magnitude that prevents the two-terminal switching element from being set to the on-state, to the memory cell.

公开(公告)号：US20240112732A1

公开(公告)日：2024-04-04

申请号：US18460493

申请日：2023-09-01

Applicant: Kioxia Corporation

Inventor： Yu SHIMADA ,  Ryousuke TAKIZAWA ,  Akira KATAYAMA

IPC: G11C13/00

CPC classification number: G11C13/0069 ,  G11C13/0038 ,  G11C13/004

Abstract: A memory device includes a memory cell connected between first and second signal lines, a first wiring connected to the first signal line, a second wiring connected to the second signal line, and a precharging circuit connected to the first wiring. During a write sequence, the precharging circuit charges the first signal line and the first wiring, the memory cell is activated according to a voltage difference between the first signal line and the second signal line, and a write current generated from parasitic capacitances of both the charged first signal line and the charged first wiring flows from the first wiring to the second wiring via the activated memory cell.

公开(公告)号：US20210295890A1

公开(公告)日：2021-09-23

申请号：US17021173

申请日：2020-09-15

Applicant: Kioxia Corporation

Inventor： Ryousuke TAKIZAWA

IPC: G11C11/16

Abstract: According to one embodiment, a memory device includes first and second lines, a memory cell connected between the first and second lines, and including a resistance change memory element and a switching element, a current supply circuit supplying write current to the memory cell when data is written to the resistance change memory element, a detection circuit detecting an on state of the switching element after supply operation of the write current is enabled, and a control circuit controlling a time required until supplying the write current from the current supply circuit is stopped, wherein a starting point of the controlling the time is a time point at which the on state of the switching element is detected.