公开(公告)号：US20210201973A1

公开(公告)日：2021-07-01

申请号：US17005149

申请日：2020-08-27

Applicant: KIOXIA CORPORATION

Inventor： Akira KATAYAMA

IPC: G11C11/16 ,  H01L27/22

Abstract: A semiconductor storage device includes a memory cell including a switching element and a variable resistance element, and a circuit for switching the memory cell ON, performing a first read operation on the memory cell, generating a first voltage based on the first read operation, switching the memory cell ON after first data is written to the memory cell, performing a second read operation while the memory cell is maintained to be ON when the first data is stored in the memory cell during the first read operation, performing the second read operation after the memory cell transitions from ON to OFF at least once when second data is stored in the memory cell during the first read operation, generating a second voltage based on the second read operation, and determining the data stored in the memory cell during the first read operation based on the first and second voltages.

公开(公告)号：US20240112732A1

公开(公告)日：2024-04-04

申请号：US18460493

申请日：2023-09-01

Applicant: Kioxia Corporation

Inventor： Yu SHIMADA ,  Ryousuke TAKIZAWA ,  Akira KATAYAMA

IPC: G11C13/00

CPC classification number: G11C13/0069 ,  G11C13/0038 ,  G11C13/004

Abstract: A memory device includes a memory cell connected between first and second signal lines, a first wiring connected to the first signal line, a second wiring connected to the second signal line, and a precharging circuit connected to the first wiring. During a write sequence, the precharging circuit charges the first signal line and the first wiring, the memory cell is activated according to a voltage difference between the first signal line and the second signal line, and a write current generated from parasitic capacitances of both the charged first signal line and the charged first wiring flows from the first wiring to the second wiring via the activated memory cell.

公开(公告)号：US20230410853A1

公开(公告)日：2023-12-21

申请号：US18178135

申请日：2023-03-03

Applicant: Kioxia Corporation

Inventor： Akira KATAYAMA ,  Kosuke HATSUDA

IPC: G11C7/06 ,  G11C7/10 ,  G11C5/06

CPC classification number: G11C7/067 ,  G11C7/1069 ,  G11C5/063

Abstract: A memory system according to an embodiment includes a plurality of first wirings, a plurality of second wirings, a memory cell, a third wiring, a sense amplifier, a first switching element, a first transistor including a first terminal connected to a first node and a second terminal connected to a second node, and a control circuit. The first node is positioned further to the side of the sense amplifier than the first switching element. The second node is positioned further to the memory cell than the first switching element. The control circuit is configured to connect the first node and the second node when the first switching element is in an ON state, and connect the first node and the gate terminal of the first transistor when the first switching element is in an OFF state.

公开(公告)号：US20220084575A1

公开(公告)日：2022-03-17

申请号：US17200966

申请日：2021-03-15

Applicant: Kioxia Corporation

Inventor： Akira KATAYAMA

IPC: G11C11/16

Abstract: According to one embodiment, a device includes a sense amplifier sensing a first signal based on first data in a cell and a second signal based on second data in the cell. The sense amplifier includes a current mirror causing a first current to flow in a first node connected to the cell and a second current in a second node based on a potential of the first node, a first switch connected to the second node and a third node, a transistor including a terminal connected to the second node and a gate connected to the third node, a second switch connected to the second node and a fourth node, and a circuit connected to the second and third node and causing a third current to flow in the second node based on a potential of the third node.

公开(公告)号：US20240312506A1

公开(公告)日：2024-09-19

申请号：US18599986

申请日：2024-03-08

Applicant: Kioxia Corporation

Inventor： Akira KATAYAMA

IPC: G11C11/16

CPC classification number: G11C11/1673 ,  G11C11/161

Abstract: A memory cell includes first and second ends. A first interconnect is coupled to the first end. A first switch is coupled between the first interconnect and a first node that receives a first voltage. A second interconnect is coupled to the second end. A second switch includes a third end coupled to the second interconnect and a fourth end. A third interconnect is coupled to the fourth end. A third switch is coupled between the third interconnect and a second node that receives a second voltage different from the first voltage. A third voltage between the second and first voltages is applied to the first and second interconnects. The third and second switches are respectively turned off and on after the third switch is turned on and after the application of the third voltage. The first switch is turned off after the application of the third voltage.

公开(公告)号：US20230087475A1

公开(公告)日：2023-03-23

申请号：US17684502

申请日：2022-03-02

Applicant: Kioxia Corporation

Inventor： Akira KATAYAMA

IPC: G11C13/00 ,  G11C5/06

Abstract: A memory system according to an embodiment includes a first wiring, a second wiring, a memory cell between the first wiring and the second wiring and a controller. The memory cell includes a variable resistance element and a switching element. The variable resistance element is switchable between a first low-resistance state and a first high-resistance state. The switching element is switchable between a second low-resistance state and a second high-resistance state in accordance with a supplied voltage. The controller is configured to supply the first wiring with a first voltage switching the switching element to the second low-resistance state, supply the first wiring with a second voltage switching the switching element from the second low-resistance state to the second high-resistance state after the first voltage is supplied, and detect a first target voltage of the second wiring after the second voltage is supplied.

公开(公告)号：US20220293155A1

公开(公告)日：2022-09-15

申请号：US17462449

申请日：2021-08-31

Applicant: KIOXIA CORPORATION

Inventor： Akira KATAYAMA ,  Kosuke HATSUDA

IPC: G11C11/16

Abstract: A storage device includes a first interconnection, a second interconnection, a memory cell connected between the first and second interconnections and including a variable resistance element and a switching element that is connected in series to the variable resistance element, and a control circuit configured to exercise control of a read operation to read data stored in the memory cell. The control circuit exercises control in such a manner as to set the first interconnection which has been charged with a first voltage and the second interconnection which has been charged with a second voltage into floating states, to set the switching element into an on-state by discharging the second interconnection set into the floating state to thereby increase a voltage applied to the memory cell, and to read the data stored in the memory cell in a state in which the switching element is set into the on-state.

公开(公告)号：US20230290397A1

公开(公告)日：2023-09-14

申请号：US17898913

申请日：2022-08-30

Applicant: KIOXIA CORPORATION

Inventor： Akira KATAYAMA

IPC: G11C11/16 ,  H01L27/22 ,  H01L43/02 ,  H01L43/08

CPC classification number: G11C11/161 ,  H01L27/228 ,  H01L43/02 ,  H01L43/08 ,  G11C11/1655 ,  G11C11/1657 ,  G11C11/1673 ,  G11C11/1675

Abstract: A memory device includes a first conductor, a first stacked body on the first conductor, a second conductor on the first stacked body, a second stacked body on the second conductor, and a third conductor on the second stacked body. The first stacked body includes a first ferromagnetic layer, a first insulating layer, a second ferromagnetic layer, a non-magnetic first metal layer, and a third ferromagnetic layer stacked in order from a side of the first conductor. The second and third ferromagnetic layers have magnetizations in opposite directions. The second stacked body includes a fourth ferromagnetic layer, a second insulating layer, a fifth ferromagnetic layer, a non-magnetic second metal layer, and a sixth ferromagnetic layer stacked in order from a side of the second conductor. The fifth and sixth ferromagnetic layers have magnetizations in opposite directions. The sixth ferromagnetic layer has a larger volume than the third ferromagnetic layer.