公开(公告)号：US11853599B2

公开(公告)日：2023-12-26

申请号：US17185104

申请日：2021-02-25

Applicant: KIOXIA CORPORATION

Inventor： Takeshi Nakano ,  Akihiko Ishihara ,  Shingo Tanimoto ,  Yasuaki Nakazato ,  Shinji Maeda ,  Minoru Uchida ,  Kenji Sakaue ,  Koichi Inoue ,  Yosuke Kino ,  Takumi Sasaki ,  Mikio Takasugi ,  Kouji Saitou ,  Hironori Nagai ,  Shinya Takeda ,  Akihito Touhata ,  Masaru Ogawa ,  Akira Aoki

IPC: G06F11/00 ,  G06F3/06 ,  G06F11/10

CPC classification number: G06F3/0659 ,  G06F3/0604 ,  G06F3/0679 ,  G06F11/1068

Abstract: A memory system includes a non-volatile memory and a controller that includes a first memory and is configured to write log data to the first memory, including a history of commands for controlling the memory system. An information processing system includes the memory system and an information processing device configured to store an expected value and to transmit a signal that instructs the memory system to stop when a value of the log data transmitted from the memory system does not match the expected value. The expected value and the transmitted value are determined based on the log data of the memory system.

公开(公告)号：US12164446B2

公开(公告)日：2024-12-10

申请号：US18477709

申请日：2023-09-29

Applicant: KIOXIA CORPORATION

Inventor： Kenji Sakaue ,  Toshiyuki Furusawa ,  Shinya Takeda

IPC: G06F13/16 ,  G06F13/40 ,  G06F13/42 ,  H01L23/00 ,  H01L25/065 ,  H01L25/18

Abstract: According to one embodiment, a memory system includes a first chip and a second chip. The second chip is bonded with the first chip. The memory system includes a semiconductor memory device and a memory controller. The semiconductor memory device includes a memory cell array, a peripheral circuit, and an input/output module. The memory controller is configured to receive an instruction from an external host device and control the semiconductor memory device via the input/output module. The first chip includes the memory cell array. The second chip includes the peripheral circuit, the input/output module, and the memory controller.

公开(公告)号：US11500793B2

公开(公告)日：2022-11-15

申请号：US17158134

申请日：2021-01-26

Applicant: Kioxia Corporation

Inventor： Kenji Sakaue ,  Toshiyuki Furusawa ,  Shinya Takeda

IPC: G06F13/16 ,  G06F13/40 ,  G06F13/42 ,  H01L25/065 ,  H01L25/18 ,  H01L23/00

Abstract: According to one embodiment, a memory system includes a first chip and a second chip. The second chip is bonded with the first chip. The memory system includes a semiconductor memory device and a memory controller. The semiconductor memory device includes a memory cell array, a peripheral circuit, and an input/output module. The memory controller is configured to receive an instruction from an external host device and control the semiconductor memory device via the input/output module. The first chip includes the memory cell array. The second chip includes the peripheral circuit, the input/output module, and the memory controller.

公开(公告)号：US12277348B2

公开(公告)日：2025-04-15

申请号：US18501943

申请日：2023-11-03

Applicant: Kioxia Corporation

Inventor： Takeshi Nakano ,  Akihiko Ishihara ,  Shingo Tanimoto ,  Yasuaki Nakazato ,  Shinji Maeda ,  Minoru Uchida ,  Kenji Sakaue ,  Koichi Inoue ,  Yosuke Kino ,  Takumi Sasaki ,  Mikio Takasugi ,  Kouji Saitou ,  Hironori Nagai ,  Shinya Takeda ,  Akihito Touhata ,  Masaru Ogawa ,  Akira Aoki

IPC: G06F3/06 ,  G06F11/10

Abstract: A memory system includes a non-volatile memory and a controller that includes a first memory and is configured to write log data to the first memory, including a history of commands for controlling the memory system. An information processing system includes the memory system and an information processing device configured to store an expected value and to transmit a signal that instructs the memory system to stop when a value of the log data transmitted from the memory system does not match the expected value. The expected value and the transmitted value are determined based on the log data of the memory system.

公开(公告)号：US11853238B2

公开(公告)日：2023-12-26

申请号：US17943798

申请日：2022-09-13

Applicant: Kioxia Corporation

Inventor： Kenji Sakaue ,  Toshiyuki Furusawa ,  Shinya Takeda

IPC: G06F13/16 ,  G06F13/40 ,  G06F13/42 ,  H01L25/065 ,  H01L25/18 ,  H01L23/00

CPC classification number: G06F13/1668 ,  G06F13/4022 ,  G06F13/4282 ,  H01L23/562 ,  H01L25/0657 ,  H01L25/18 ,  H01L2225/0652 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06586

Abstract: According to one embodiment, a memory system includes a first chip and a second chip. The second chip is bonded with the first chip. The memory system includes a semiconductor memory device and a memory controller. The semiconductor memory device includes a memory cell array, a peripheral circuit, and an input/output module. The memory controller is configured to receive an instruction from an external host device and control the semiconductor memory device via the input/output module. The first chip includes the memory cell array. The second chip includes the peripheral circuit, the input/output module, and the memory controller.

公开(公告)号：US11416153B2

公开(公告)日：2022-08-16

申请号：US17010772

申请日：2020-09-02

Applicant: KIOXIA CORPORATION

Inventor： Tetsuya Iwata ,  Hiroya Shirakura ,  Shinya Takeda

IPC: G06F3/06

Abstract: A memory system of an embodiment includes a non-volatile memory and a controller configured to control the accessing of the non-volatile memory according to commands from a host device. The controller is configured to set a mode transition time to a value according to a first command received from the host. The controller transitions from a first operating mode to a second operating mode, in which power supply is suspended to a predetermined circuit, when the time since the last command was received from the host device reaches the mode transition time. The controller maintains the second operating mode until another command is received from the host device.

公开(公告)号：US11360676B2

公开(公告)日：2022-06-14

申请号：US17003840

申请日：2020-08-26

Applicant: KIOXIA CORPORATION

Inventor： Hiroya Shirakura ,  Shinya Takeda

IPC: G06F3/06 ,  G11C16/04 ,  G11C16/30

Abstract: According to one or more embodiments, a memory system includes a signal terminal, a power line, a resistance element, a nonvolatile semiconductor memory, and a controller. The resistance element is provided between the signal terminal and the power line. The nonvolatile semiconductor memory is configured to transmit and receive a signal to and from a host device via the signal terminal. The controller is configured to determine whether to connect the signal terminal to the power line via the resistance element.