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    Memory system
    4.
    发明授权
    Memory system 有权

    公开(公告)号：US11798605B2

    公开(公告)日：2023-10-24

    申请号：US17470411

    申请日：2021-09-09

    Applicant: Kioxia Corporation

    Inventor： Kenji Sakaue

    IPC: G11C7/22 ,  G11C7/10

    CPC classification number: G11C7/222 ,  G11C7/1003 ,  G11C7/109 ,  G11C7/1048 ,  G11C7/1063

    Abstract: According to one embodiment, there is provided a memory system including a controller, a plurality of memory chips, and a channel. The controller outputs a clock signal, a timing control signal and a data signal. Each of the plurality of memory chips includes at least a clock input terminal, a timing control input terminal, a timing control output terminal, a data input terminal and a data output terminal. The channel includes a loop bus which connects the controller and the plurality of memory chips in a ring shape. The controller is able to control operation timings of the memory chips by transmitting the clock signal and the timing control signal to the plurality of memory chips via the channel.

    Memory controller, memory system, and control method of memory system
    5.
    发明授权
    Memory controller, memory system, and control method of memory system 有权

    公开(公告)号：US11520719B2

    公开(公告)日：2022-12-06

    申请号：US17190757

    申请日：2021-03-03

    Applicant: KIOXIA CORPORATION

    Inventor： Tamio Saimen ,  Kenji Sakaue

    IPC: G06F13/16 ,  G06F13/42

    Abstract: A memory controller includes a host interface circuit connectable to a host device by a bus conforming to a memory card system specification, a data buffer circuit including a buffer memory, a tag information generation circuit configured to generate tag information associated with a command received by the host interface circuit, and a first register in which the tag information generated by the tag information generation circuit is stored, and a second register into which the tag information stored in the first register is copied after the command is fetched from the host interface circuit for processing. When a read request is made from the host interface circuit to the data buffer circuit, the data buffer circuit returns read data stored in the buffer memory upon confirming that the tag information stored in the first register and the tag information stored in the second register match each other.

    Memory system
    6.
    发明授权
    Memory system 有权

    公开(公告)号：US11500793B2

    公开(公告)日：2022-11-15

    申请号：US17158134

    申请日：2021-01-26

    Applicant: Kioxia Corporation

    Inventor： Kenji Sakaue ,  Toshiyuki Furusawa ,  Shinya Takeda

    IPC: G06F13/16 ,  G06F13/40 ,  G06F13/42 ,  H01L25/065 ,  H01L25/18 ,  H01L23/00

    Abstract: According to one embodiment, a memory system includes a first chip and a second chip. The second chip is bonded with the first chip. The memory system includes a semiconductor memory device and a memory controller. The semiconductor memory device includes a memory cell array, a peripheral circuit, and an input/output module. The memory controller is configured to receive an instruction from an external host device and control the semiconductor memory device via the input/output module. The first chip includes the memory cell array. The second chip includes the peripheral circuit, the input/output module, and the memory controller.

    Memory system
    7.
    发明授权
    Memory system 有权

    公开(公告)号：US12164446B2

    公开(公告)日：2024-12-10

    申请号：US18477709

    申请日：2023-09-29

    Applicant: KIOXIA CORPORATION

    Inventor： Kenji Sakaue ,  Toshiyuki Furusawa ,  Shinya Takeda

    IPC: G06F13/16 ,  G06F13/40 ,  G06F13/42 ,  H01L23/00 ,  H01L25/065 ,  H01L25/18

    Abstract: According to one embodiment, a memory system includes a first chip and a second chip. The second chip is bonded with the first chip. The memory system includes a semiconductor memory device and a memory controller. The semiconductor memory device includes a memory cell array, a peripheral circuit, and an input/output module. The memory controller is configured to receive an instruction from an external host device and control the semiconductor memory device via the input/output module. The first chip includes the memory cell array. The second chip includes the peripheral circuit, the input/output module, and the memory controller.

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